R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 641

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Bit
7
6
5
4
Bit Name
TIE
RIE
TE
RE
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
A TXI interrupt request can be cancelled by reading 1
from the TDRE flag and then clearing the flag to 0, or by
clearing the TIE bit to 0.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
RXI and ERI interrupt requests can be cancelled by
reading 1 from the RDRF, FER, PER, or ORER flag and
then clearing the flag to 0, or by clearing the RIE bit to
0.
Transmit Enable
When this bit is set to 1, transmission is enabled. Under
this condition, serial transmission is started by writing
transmit data to TDR, and clearing the TDRE flag in
SSR to 0. Note that SMR should be set prior to setting
the TE bit to 1 in order to designate the transmission
format.
If transmission is halted by clearing this bit to 0, the
TDRE flag in SSR is fixed 1.
Receive Enable
When this bit is set to 1, reception is enabled. Under
this condition, serial reception is started by detecting
the start bit in asynchronous mode or the synchronous
clock input in clocked synchronous mode. Note that
SMR should be set prior to setting the RE bit to 1 in
order to designate the reception format.
Even if reception is halted by clearing this bit to 0, the
RDRF, FER, PER, and ORER flags are not affected
and the previous value is retained.
Section 16 Serial Communication Interface (SCI)
Rev. 2.00 Sep. 16, 2009 Page 611 of 1036
REJ09B0414-0200

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