R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 654

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface (SCI)
16.3.8
SCMR selects smart card interface mode and its format.
Rev. 2.00 Sep. 16, 2009 Page 624 of 1036
REJ09B0414-0200
Bit
7 to 4
3
2
1
0
Bit
Bit Name
Initial Value
R/W
Smart Card Mode Register (SCMR)
Bit Name

SDIR
SINV

SMIF

R
7
1
Initial
Value
All 1
0
0
1
0

R
6
1
R/W
R
R/W
R/W
R
R/W

R
5
1
Description
Reserved
These are read-only bits and cannot be modified.
Smart Card Data Transfer Direction
Selects the serial/parallel conversion format.
0: Transfer with LSB-first
1: Transfer with MSB-first
This bit is valid only when the 8-bit data format is used
for transmission/reception; when the 7-bit data format is
used, data is always transmitted/received with LSB-first.
Smart Card Data Invert
Inverts the transmit/receive data logic level. This bit
does not affect the logic level of the parity bit. To invert
the parity bit, invert the O/E bit in SMR.
0: TDR contents are transmitted as they are. Receive
1: TDR contents are inverted before being transmitted.
Reserved
This is a read-only bit and cannot be modified.
Smart Card Interface Mode Select
When this bit is set to 1, smart card interface mode is
selected.
0: Normal asynchronous or clocked synchronous mode
1: Smart card interface mode
data is stored as it is in RDR.
Receive data is stored in inverted form in RDR.

R
4
1
SDIR
R/W
3
0
SINV
R/W
2
0

R
1
1
SMIF
R/W
0
0