R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 686

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 16 Serial Communication Interface (SCI)
16.6.3
Figure 16.16 shows an example of the operation for transmission in clocked synchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
3. 8-bit data is sent from the TxD pin synchronized with the output clock when clock output
4. The SCI checks the TDRE flag at the timing for sending the last bit.
5. If the TDRE flag is cleared to 0, the next transmit data is transferred from TDR to TSR, and
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin retains the
Figure 16.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
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REJ09B0414-0200
TDR, and transfers the data from TDR to TSR.
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated.
Because the TXI interrupt processing routine writes the next transmit data to TDR before
transmission of the current transmit data has finished, continuous transmission can be enabled.
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
serial transmission of the next frame is started.
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request
is generated. The SCK pin is fixed high.
Serial Data Transmission (Clocked Synchronous Mode)