R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 695

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

16.7.4
Only the internal clock generated by the on-chip baud rate generator can be used as a transfer
clock in smart card interface mode. In this mode, the SCI can operate on a basic clock with a
frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 bit settings
(the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the
falling edge of the start bit is sampled using the basic clock in order to perform internal
synchronization. Receive data is sampled on the 16th, 32nd, 186th and 128th rising edges of the
basic clock so that it can be latched at the middle of each bit as shown in figure 16.25. The
reception margin here is determined by the following formula.
Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin is
determined by the formula below.
Internal
basic clock
Receive data
(RxD)
Synchronization
sampling timing
Data sampling
timing
Figure 16.25 Receive Data Sampling Timing in Smart Card Interface Mode
M: Reception margin (%)
N: Ratio of bit rate to clock (N = 32, 64, 372, 256)
D: Duty cycle of clock (D = 0 to 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
M =
M = | (0.5 –
Receive Data Sampling Timing and Reception Margin
( 0.5 –
(When Clock Frequency is 372 Times the Bit Rate)
2 × 372
0
2N
1
186 clock
cycles
1
) – (L – 0.5) F –
372 clock cycles
185
) × 100% = 49.866%
Start bit
371
| D – 0.5 |
0
N
D0
Section 16 Serial Communication Interface (SCI)
(1 + F ) | × 100%
Rev. 2.00 Sep. 16, 2009 Page 665 of 1036
185
371 0
REJ09B0414-0200
D1