R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 722

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 17 I
17.3.5
ICSR confirms the interrupt request flags and status.
Rev. 2.00 Sep. 16, 2009 Page 692 of 1036
REJ09B0414-0200
Bit
7
6
Bit
Bit Name
Initial Value
R/W
I
Bit Name
TDRE
TEND
2
2
C Bus Status Register (ICSR)
C Bus Interface 2 (IIC2)
TDRE
R/W
7
0
Initial
Value
0
0
TEND
R/W
6
0
R/W
R/W
R/W
RDRF
R/W
5
0
Description
Transmit Data Register Empty
[Setting conditions]
•
•
•
•
[Clearing conditions]
•
•
Transmit End
[Setting condition]
•
[Clearing conditions]
•
•
NACKF
When data is transferred from ICDRT to ICDRS
and ICDRT becomes empty
When the TRS bit is set
When a start condition (that includes a retransmit
condition) is issued
When the slave receive mode shifts to the slave
transmit mode
When 0 is written to this bit after reading TDRE = 1
(When the CPU is used to clear this flag by writing
0 while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When data is written to ICDRT
When the ninth clock of SCL rises while the TDRE
flag is 1
When 0 is written to this bit after reading TEND = 1
(When the CPU is used to clear this flag by writing
0 while the corresponding interrupt is enabled, be
sure to read the flag after writing 0 to it.)
When data is written to ICDRT
R/W
4
0
STOP
R/W
3
0
R/W
AL
2
0
AAS
R/W
1
0
ADZ
R/W
0
0