R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 728

KIT STARTER FOR H8SX/1622

R0K561622S000BE

Manufacturer Part Number
R0K561622S000BE
Description
KIT STARTER FOR H8SX/1622
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K561622S000BE

Contents
Board, Cables, CD, Debugger, Power Supply
Silicon Manufacturer
Renesas
Features
Coding And Debugging, E10A Emulator, RS232 Serial Connection
Kit Contents
Board
Silicon Family Name
H8SX/1622F
Silicon Core Number
R5F61622N50LGV
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With/related Products
H8SX/1622
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Section 17 I
17.4.2
In I
data, and the slave device return an acknowledge signal. Figures 17.5 and 17.6 show the operating
timings in master transmit mode. The transmission procedure and operations in master transmit
mode are described below.
1. Set the ICR bit in the corresponding register to 1. Set the ICE bit in ICCRA to 1. Set the WAIT
2. Read the BSSY flag in ICCRB to confirm that the bus is free. Set the MST and TRS bits in
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte shows
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
5. The transmit data after the second byte is written to ICDRT every time TDRE is set.
6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last
7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
Rev. 2.00 Sep. 16, 2009 Page 698 of 1036
REJ09B0414-0200
2
bit in ICMR and the CKS3 to CKS0 bits in ICCRA to 1. (initial setting)
ICCRA to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using the MOV
instruction. (The start condition is issued.) This generates the start condition.
the slave address and R/W) to ICDRT. After this, when TDRE is automatically cleared to 0,
data is transferred from ICDRT to ICDRS. TDRE is set again.
at the rising of the ninth transmit clock pulse. Read the ACKBR bit in ICIER to confirm that
the slave device has been selected. Then, write the second byte data to ICDRT. When ACKBR
is 1, the slave device has not been acknowledged, so issue a stop condition. To issue the stop
condition, write 0 to BBSY and SCP using the MOV instruction. SCL is fixed to a low level
until the transmit data is prepared or the stop condition is issued.
byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR is 1) from the
receive device while CKE in ICIER is 1. Then, issue the stop condition to clear TEND or
NACKF.
C bus format master transmit mode, the master device outputs the transmit clock and transmit
Master Transmit Operation
2
C Bus Interface 2 (IIC2)

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