R0K561622S000BE Renesas Electronics America, R0K561622S000BE Datasheet - Page 844

• Manufacturer Part Number: R0K561622S000BE
• Description: KIT STARTER FOR H8SX/1622
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K561622S000BE

• Contents: Board, Cables, CD, Debugger, Power Supply
• Silicon Manufacturer: Renesas
• Features: Coding And Debugging, E10A Emulator, RS232 Serial Connection
• Kit Contents: Board
• Silicon Family Name: H8SX/1622F
• Silicon Core Number: R5F61622N50LGV
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: H8SX/1622
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

Section 22 Flash Memory
4. FKEY is cleared to H'00 for protection.
5. The download result must be confirmed by the value of the DPFR parameter. Check the value
6. The operating frequency of the CPU is set in the FPEFEQ parameter for initialization. The
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 The return value is set in the DPFR parameter.
 After the on-chip program storage area is returned to the user-MAT space, the procedure
 During download, the values of general registers other than ER0 and ER1 are held.
 During download, no interrupts can be accepted. However, since the interrupt requests are
 To hold a level-detection interrupt request, the interrupt must continue to be input until the
 Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the
 If access to the flash memory is requested by the DMAC or DTC during download, the
of the DPFR parameter (one byte of start address of the download destination specified by
FTDAR). If the value of the DPFR parameter is H'00, download has been performed normally.
If the value is not H'00, the source that caused download to fail can be investigated by the
description below.
 If the value of the DPFR parameter is the same as that before downloading, the setting of
 If the value of the DPFR parameter is different from that before downloading, check the SS
settable operating frequency of the FPEFEQ parameter ranges from 8 to 50 MHz. When the
frequency is set otherwise, an error is returned to the FPFR parameter of the initialization
program and initialization is not performed. For details on setting the frequency, see section
22.7.2 (3), Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of
CPU).
program is resumed. After that, VBR can be set again.
held, when the procedure program is resumed, the interrupts are requested.
download is completed.
SCO bit to 1.
operation cannot be guaranteed. Make sure that an access request by the DMAC or DTC is
not generated.
the start address of the download destination in FTDAR may be abnormal. In this case,
confirm the setting of the TDER bit in FTDAR.
bit or FK bit in the DPFR parameter to confirm the download program selection and FKEY
setting, respectively.