Z8F08200100KIT Zilog, Z8F08200100KIT Datasheet - Page 128

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Z8F08200100KIT

Manufacturer Part Number
Z8F08200100KIT
Description
DEV KIT FOR Z8 ENCORE 4K TO 8K
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Datasheets

Specifications of Z8F08200100KIT

Contents
Evaluation Board, Cable, Power Supply, Software and Documentation
Data Bus Width
8 bit
Interface Type
RS-485
Silicon Manufacturer
Zilog
Core Architecture
Z8 Encore
Silicon Core Number
Z8F0822SJ020
Silicon Family Name
XP F0822
For Use With/related Products
Z8 Encore!™
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
269-3183
PS022517-0508
SPI Signals
During an SPI transfer, data is sent and received simultaneously by both the Master and
the Slave SPI devices. Separate signals are required for data and the serial clock. When an
SPI transfer occurs, a multi-bit (typically 8-bit) character is shifted out one data pin and an
multi-bit character is simultaneously shifted in on a second data pin. An 8-bit shift register
in the Master and another 8-bit shift register in the Slave are connected as a circular buffer.
The SPI shift register is single-buffered in the transmit and receive directions. New data to
be transmitted cannot be written into the shift register until the previous transmission is
complete and receive data (if valid) has been read.
The four basic SPI signals are:
The following sections discuss these SPI signals. Each signal is described in both
Master and Slave modes.
Master-In/Slave-Out
The Master-In/Slave-Out (MISO) pin is configured as an input in a Master device and as
an output in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. The MISO pin of a Slave device is placed in a high-impedance
state if the Slave is not selected. When the SPI is not enabled, this signal is in a high-
impedance state.
Master-Out/Slave-In
The Master-Out/Slave-In (MOSI) pin is configured as an output in a Master device and as
an input in a Slave device. It is one of the two lines that transfer serial data, with the most
significant bit sent first. When the SPI is not enabled, this signal is in a high-impedance
state.
Serial Clock
The Serial Clock (SCK) synchronizes data movement both in and out of the device
through its MOSI and MISO pins. In MASTER mode, the SPI’s Baud Rate Generator
creates the serial clock. The Master drives the serial clock out its own SCK pin to the
Slave’s SCK pin. When the SPI is configured as a Slave, the SCK pin is an input and the
clock signal from the Master synchronizes the data transfer between the Master and Slave
devices. Slave devices ignore the SCK signal, unless the SS pin is asserted. When config-
ured as a slave, the SPI block requires a minimum SCK period of greater than or equal to 8
times the system (XIN) clock period.
MISO (Master-In, Slave-Out)
MOSI (Master-Out, Slave-In)
SCK (Serial Clock)
SS (Slave Select)
Z8 Encore! XP
Product Specification
Serial Peripheral Interface
®
F0822 Series
115

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