Z8F08200100KIT Zilog, Z8F08200100KIT Datasheet - Page 142

• Manufacturer Part Number: Z8F08200100KIT
• Description: DEV KIT FOR Z8 ENCORE 4K TO 8K
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F08200100KIT

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Data Bus Width: 8 bit
• Interface Type: RS-485
• Silicon Manufacturer: Zilog
• Core Architecture: Z8 Encore
• Silicon Core Number: Z8F0822SJ020
• Silicon Family Name: XP F0822
• For Use With/related Products: Z8 Encore!™
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3183

PS022517-0508
Note:
Software Control of I
Caution:
Writing to the I
the I
shifting out until the data register is written with the next value to send or the STOP or
START bits are set indicating the current byte is the last one to send.
Receive interrupts occur when a byte of data has been received by the I
(Master reading data from Slave). This procedure sets the RDRF bit of the I
Register. The RDRF bit is cleared by reading the I
during the acknowledge phase. The I
until the receive interrupt is cleared before performing any other action.
Transmit interrupts occur when the TDRE bit of the I
bit in the I
conditions when the Transmit Data Register is empty:
•
•
•
•
The fourth interrupt source is the BRG. If the I
I2CCTL Register = 0) and the BIRQ bit in the I2CCTL Register = 1,
an interrupt is generated when the BRG counts down to 1. This allows the I
Generator to be used by software as a general purpose timer when IEN = 0.
Software controls I
Status register or by DMA. Note that not all products include a DMA Controller.
To use interrupts, the I
in the I
To control transactions by polling, the interrupt bits (TDRE, RDRF and NCKI) in the
I
TXI bit.
Either or both transmit and receive data movement can be controlled by the DMA
Controller. The DMA Controller channel(s) must be initialized to select the I
and receive requests. Transmit DMA requests require that the TXI bit in the I
Register be set.
2
C Status Register should be polled. The TDRE bit asserts regardless of the state of the
2
The I
The first bit of the byte of an address is shifting out and the RD bit of the I
register is deasserted.
The first bit of a 10-bit address shifts out.
The first bit of write data shifts out.
before the last byte has been sent. After receiving the Not Acknowledge, the I
troller sets the NCKI bit in the Status Register and pauses until either the STOP or
A transmit (write) DMA operation hangs if the slave responds with a Not Acknowledge
C Controller pauses at the beginning of the Acknowledge cycle of the byte currently
2
C Control Register must be set to enable transmit interrupts.
2
2
C Controller is enabled
C Control Register is set. Transmit interrupts occur under the following
2
C Data Register always clears the TRDE bit to 0. When TDRE is asserted,
2
2
C Transactions
C transactions by using the I
2
C interrupt must be enabled in the Interrupt Controller. The TXI bit
2
C Controller pauses after the acknowledge phase
2
C Controller is disabled (IEN bit in the
2
C Controller interrupt, by polling the I
2
C Data Register. The RDRF bit is set
2
C Status register sets and the TXI
Z8 Encore! XP
Product Specification
2
C Controller
®
F0822 Series
2
2
C Baud Rate
C Status
2
2
I2C Controller
C transmit
2
C Control
C Status
2
C Con-
2
C
129