Z8F08200100KIT Zilog, Z8F08200100KIT Datasheet - Page 188

• Manufacturer Part Number: Z8F08200100KIT
• Description: DEV KIT FOR Z8 ENCORE 4K TO 8K
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F08200100KIT

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Data Bus Width: 8 bit
• Interface Type: RS-485
• Silicon Manufacturer: Zilog
• Core Architecture: Z8 Encore
• Silicon Core Number: Z8F0822SJ020
• Silicon Family Name: XP F0822
• For Use With/related Products: Z8 Encore!™
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3183

PS022517-0508
Breakpoints
The host transmits a Serial Break on the
Z8 Encore! XP
from the host resets the Auto-Baud Generator/Detector but does not reset the OCD Con-
trol Register. A Serial Break leaves the device in DEBUG mode if that is the current mode.
The OCD is held in Reset until the end of the Serial Break when the DBG pin returns
High. Because of the open-drain nature of the
the OCD even if the OCD is transmitting a character.
Execution Breakpoints are generated using the BRK instruction (opcode
eZ8 CPU decodes a BRK instruction, it signals the OCD. If Breakpoints are enabled, the
OCD idles the eZ8 CPU and enters DEBUG mode. If Breakpoints are not enabled, the
OCD ignores the BRK signal and the BRK instruction operates as an NOP instruction.
If breakpoints are enabled, the OCD can be configured to automatically enter DEBUG
mode, or to loop on the break instruction. If the OCD is configured to loop on the BRK
instruction, then the CPU is still enabled to service DMA and interrupt requests.
The loop on BRK instruction can be used to service interrupts in the background. For
interrupts to be serviced in the background, there cannot be any breakpoints in the ISR.
Otherwise, the CPU stops on the breakpoint in the interrupt routine. For interrupts to be
serviced in the background, interrupts must also be enabled. Debugging software should
not automatically enable interrupts when using this feature, since interrupts are typically
disabled during critical sections of code where interrupts should not occur (such as adjust-
ing the stack pointer or modifying shared data).
Software can poll the IDLE bit of the OCDSTAT register to determine if the OCD is loop-
ing on a BRK instruction. When software wants to stop the CPU on the BRK instruction it
is looping on, software should not set the DBGMODE bit of the OCDCTL register. The
CPU can have vectored to and be in the middle of an ISR when this bit gets set. Instead,
software must clear the BRKLP bit. This allows the CPU to finish the ISR it is in and
return the BRK instruction. When the CPU returns to the BRK instruction it was previ-
ously looping on, it automatically sets the DBGMODE bit and enter DEBUG mode.
Software should also note that the majority of the OCD commands are still disabled when
the eZ8 CPU is looping on a BRK instruction. The eZ8 CPU must be stopped and the part
must be in DEBUG mode before these commands can be issued.
Breakpoints in Flash Memory
The BRK instruction is opcode
byte in Flash memory. To implement a Breakpoint, write
writing the current instruction. To remove a Breakpoint, the corresponding page of Flash
memory must be erased and reprogrammed with the original data.
®
F0822 Series device or when recovering from an error. A Serial Break
00H
, which corresponds to the fully programmed state of a
DBG
pin when first connecting to the
DBG
pin, the host can send a Serial Break to
Z8 Encore! XP
00H
to the desired address, over-
Product Specification
®
00H
On-Chip Debugger
F0822 Series
). When the
175