Z8F08200100KIT Zilog, Z8F08200100KIT Datasheet - Page 97

• Manufacturer Part Number: Z8F08200100KIT
• Description: DEV KIT FOR Z8 ENCORE 4K TO 8K
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F08200100KIT

• Contents: Evaluation Board, Cable, Power Supply, Software and Documentation
• Data Bus Width: 8 bit
• Interface Type: RS-485
• Silicon Manufacturer: Zilog
• Core Architecture: Z8 Encore
• Silicon Core Number: Z8F0822SJ020
• Silicon Family Name: XP F0822
• For Use With/related Products: Z8 Encore!™
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3183

PS022517-0508
Watchdog Timer Refresh
Watchdog Timer Time-Out Response
When first enabled, the WDT is loaded with the value in the WDT Reload registers. The
WDT then counts down to
CPU. Execution of the WDT instruction causes the downcounter to be reloaded with the
WDT Reload value stored in the WDT Reload registers. Counting resumes following the
reload operation.
When Z8 Encore! XP
OCD), the WDT is continuously refreshed to prevent spurious WDT time-outs.
The WDT times out when the counter reaches
either an Interrupt or a Reset. The
of the WDT. For information regarding programming of the
Option Bits
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the WDT issues an interrupt
request to the interrupt controller and sets the
If interrupts are enabled, the eZ8 CPU responds to the interrupt request by fetching the
WDT interrupt vector and executing the code from the vector address. After time-out and
interrupt generation, the WDT counter rolls over to its maximum value of
continues counting. The WDT counter is not automatically returned to its Reload Value.
WDT Reset in STOP Mode
If enabled in STOP mode and configured to generate a Reset when a time-out occurs and
the device is in STOP mode, the WDT initiates a Stop Mode Recovery. Both the
status bit and the
WDT time-out in STOP mode. For more information, see
on page 39. Default operation is for the WDT and its RC oscillator to be enabled during
STOP mode.
To minimize power consumption in STOP mode, the WDT and its RC oscillator is
disabled in STOP mode. The following sequence configures the WDT to be disabled when
the Z8F082x family device enters STOP mode following execution of a STOP instruction:
1. Write
2. Write
3. Write
and its oscillator to be disabled during STOP mode. Alternatively, write
WDTCTL as the third step in this sequence to reconfigure the WDT and its oscillator
to be enabled during STOP mode. This sequence only affects WDT operation in STOP
mode.
81H
55H
AAH
on page 163.
to the Watchdog Timer Control Register (WDTCTL) to configure the WDT
to the Watchdog Timer Control Register (WDTCTL).
to the Watchdog Timer Control Register (WDTCTL).
STOP
®
bit in the WDT Control Register is set to 1 following the
F0822 Series device is operating in DEBUG Mode (using the
000000H
WDT_RES
unless a WDT instruction is executed by the eZ8
Option Bit determines the time-out response
WDT
000000H
Status Bit in the WDT Control Register.
Z8 Encore! XP
. A WDT time-out generates
Reset and Stop Mode Recovery
WDT_RES
Product Specification
Option Bit, see
®
FFFFFH
F0822 Series
Watchdog Timer
00H
WDT
to the
and
84