C8051F326-TB Silicon Laboratories Inc, C8051F326-TB Datasheet - Page 43
C8051F326-TB
Manufacturer Part Number
C8051F326-TB
Description
BOARD PROTOTYPING W/C8051F326
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F326-TB.pdf
(140 pages)
Specifications of C8051F326-TB
Contents
Board
Processor To Be Evaluated
C8051F326/F327
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F326
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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6.2.6. Special Function Registers
The direct-access data memory locations from 0x80 to 0xFF constitute the special function registers
(SFRs). The SFRs provide control and data exchange with the CIP-51's resources and peripherals. The
CIP-51 duplicates the SFRs found in a typical 8051 implementation as well as implementing additional
SFRs used to configure and access the sub-systems unique to the MCU. This allows the addition of new
functionality while retaining compatibility with the MCS-51™ instruction set. Table 6.2 lists the SFRs imple-
mented in the CIP-51 System Controller.
The SFR registers are accessed anytime the direct addressing mode is used to access memory locations
from 0x80 to 0xFF. SFRs with addresses ending in 0x0 or 0x8 (e.g., P0, TCON, SCON0, IE, etc.) are bit-
addressable as well as byte-addressable. All other SFRs are byte-addressable only. Unoccupied
addresses in the SFR space are reserved for future use. Accessing these areas will have an indeterminate
effect and should be avoided. Refer to the corresponding pages of the data sheet, as indicated in
Table 6.3, for a detailed description of each register.
E8
E0
D8
D0
C8
C0
B8
B0
A8
A0
SFRs are listed in alphabetical order. All undefined SFR locations are reserved.
Register
ACC
B
CKCON
CLKMUL
CLKSEL
DPH
DPL
EIE1
F8
F0
98
90
88
80
(bit addressable)
SCON0
TCON
PSW
ACC
0(8)
P3
P2
P0
IP
IE
B
Address
Table 6.2. Special Function Register (SFR) Memory Map
REG0CN
CLKMUL
SBCON0
CLKSEL
SBUF0
TMOD
0xE0
0x8E
0xA9
0xE6
0xF0
0x91
0x83
0x82
1(9)
SP
Table 6.3. Special Function Registers
GPIOCN
OSCICN
EMI0CN
SMOD0
Description
Accumulator
B Register
Clock Control
Clock Multiplier
Clock Select
Data Pointer High
Data Pointer Low
Extended Interrupt Enable 1
DPL
2(A)
TL0
OSCLCN
OSCICL
SBRLL0
DPH
3(B)
TL1
Rev. 1.1
P0MDOUT
SBRLH0
TH0
4(C)
TH1
5(D)
C8051F326/7
P2MDOUT
USB0ADR
CKCON
FLSCL
EIP1
EIE1
6(E)
P3MDOUT
USB0XCN
USB0DAT
VDM0CN
RSTSRC
FLKEY
PSCTL
PCON
EIP2
EIE2
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