C8051F326-TB Silicon Laboratories Inc, C8051F326-TB Datasheet - Page 50
C8051F326-TB
Manufacturer Part Number
C8051F326-TB
Description
BOARD PROTOTYPING W/C8051F326
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F326-TB.pdf
(140 pages)
Specifications of C8051F326-TB
Contents
Board
Processor To Be Evaluated
C8051F326/F327
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F326
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F326/7
6.3.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the
data sheet section associated with a particular on-chip peripheral for information regarding valid interrupt
conditions for the peripheral and the behavior of its interrupt-pending flag(s).
50
Interrupt Source
Reset
External Interrupt 0
(/INT0)
Timer 0 Overflow
External Interrupt 1
(/INT1)
Timer 1 Overflow
UART0
USB0
VBUS Level
*Note: See Section “12.8. Interrupts” on page 101 for more details about the USB interrupt.
Interrupt
0x000B
0x001B
0x007B
0x0000
0x0003
0x0013
0x0023
0x0043
Vector
Table 6.5. Interrupt Summary
Priority
Order
Top
15
0
1
2
3
4
8
Pending Flag
None
IE0 (TCON.1)
TF0 (TCON.5)
IE1 (TCON.3)
TF1 (TCON.7)
RI0 (SCON0.0)
TI0 (SCON0.1)
Special*
N/A
Rev. 1.1
N/A N/A
N/A N/A
Y
Y
Y
Y
Y
N
N
N
Y
Y
Y
Y
Enable
Flag
Always
Enabled
EX0 (IE.0)
ET0 (IE.1) PT0 (IP.1)
EX1 (IE.2)
ET1 (IE.3) PT1 (IP.3)
ES0 (IE.4)
EUSB0
(EIE1.1)
EVBUS
(EIE2.0)
Priority
Control
Always
Highest
PX0
(IP.0)
PX1
(IP.2)
PS0
(IP.4)
PUSB0
(EIP1.1)
PVBUS
(EIP2.0)
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