C8051F326-TB Silicon Laboratories Inc, C8051F326-TB Datasheet - Page 57
C8051F326-TB
Manufacturer Part Number
C8051F326-TB
Description
BOARD PROTOTYPING W/C8051F326
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F326-TB.pdf
(140 pages)
Specifications of C8051F326-TB
Contents
Board
Processor To Be Evaluated
C8051F326/F327
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F326
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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7.
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this
reset state, the following occur:
•
•
•
•
All SFRs are reset to the predefined values noted in the SFR detailed descriptions. The contents of internal
data memory are unaffected during a reset; any previously stored data is preserved. However, since the
stack pointer SFR is reset, the stack is effectively lost even though the data on the stack is not altered.
The Port I/O latches are reset to 0xFF (all logic ones) in open-drain mode. Weak pullups are enabled dur-
ing and after the reset. For VDD Monitor and Power-On Resets, the RST pin is driven low until the device
exits the reset state.
On exit from the reset state, the program counter (PC) is reset, and the system clock defaults to the inter-
nal oscillator. Refer to Section “10. Oscillators” on page 71 for information on selecting and configuring the
system clock source. Program execution begins at location 0x0000.
XTAL2
CIP-51 halts program execution
Special Function Registers (SFRs) are initialized to their defined reset values
External Port pins are forced to a known state
Interrupts and timers are disabled.
Reset Sources
Clock Input
Frequency
Oscillator
Oscillator
External
Internal
Low
Clock Select
System
Clock
Figure 7.1. Reset Sources
Detector
Missing
Clock
(one-
shot)
Microcontroller
EN
Extended Interrupt
CIP-51
Core
Handler
VDD
Rev. 1.1
Supply
Monitor
+
-
System Reset
Enable
Power On
Reset
(Software Reset)
SWRSF
'0'
C8051F326/7
Operation
FLASH
Errant
(wired-OR)
Reset
Funnel
/RST
57
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