R0K572011S000BE Renesas Electronics America, R0K572011S000BE Datasheet - Page 784

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R0K572011S000BE

Manufacturer Part Number
R0K572011S000BE
Description
KIT STARTER FOR SH7201
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr

Specifications of R0K572011S000BE

Contents
CPU Board, LCD Display Module, E8 Emulator, Cable, QuickStart Guide and CD-ROM
For Use With/related Products
SH7201
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Section 17 I
17.4.5
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For slave receive mode operation timing, refer to
figures 17.11 and 17.12. The reception procedure and operations in slave receive mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set bits CKS[3:0] in ICCR1. (Initial setting) Set the MST and
2. When the slave address matches in the first frame following detection of the start condition,
3. Read ICDRR every time RDRF is set. If 8th receive clock pulse falls while RDRF is 1, SCL is
4. The last byte data is read by reading ICDRR.
Page 756 of 1190
(Master output)
(Master output)
(Slave output)
(Slave output)
TRS bits in ICCR1 to select slave receive mode, and wait until the slave address matches.
the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rise of the 9th
clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the
read data show the slave address and R/W, it is not used.)
fixed low until ICDRR is read. The change of the acknowledge before reading ICDRR, to be
returned to the master device, is reflected to the next transmit frame.
processing
ICDRR
ICDRS
RDRF
SCL
SDA
SDA
User
SCL
Slave Receive Operation
2
C Bus Interface 3 (IIC3)
Figure 17.11 Slave Receive Mode Operation Timing (1)
[2] Read ICDRR (dummy read)
A
9
Bit 7
1
Data 1
Bit 6
2
Bit 5
3
Bit 4
4
Bit 3
5
Bit 2
6
Bit 1
7
R01UH0026EJ0300 Rev. 3.00
Bit 0
8
[2] Read ICDRR
A
9
SH7201 Group
Sep 24, 2010
Bit 7
Data 1
1
Data 2

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