IPR-NIOS Altera, IPR-NIOS Datasheet
IPR-NIOS
Specifications of IPR-NIOS
Related parts for IPR-NIOS
IPR-NIOS Summary of contents
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... Nios II Processor Reference Handbook 101 Innovation Drive San Jose, CA 95134 www.altera.com NII5V1-10.1 Nios II Processor Reference Document last updated for Altera Complete Design Suite version: Document publication date: Handbook 10.1 December 2010 ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Configurable Cache Memory Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 Effective Use of Cache Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–14 Cache Bypass Methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 Tightly-Coupled Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–15 Accessing Tightly-Coupled Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 Effective Use of Tightly-Coupled Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 Memory Management Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–16 December 2010 Altera Corporation Contents Nios II Processor Reference Handbook ...
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... The bstatus Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 The ienable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 The ipending Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 The cpuid Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 The exception Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 The pteaddr Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–16 The tlbacc Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–17 The tlbmisc Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–18 Nios II Processor Reference Handbook Contents December 2010 Altera Corporation ...
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... Handling Nested Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–48 Nested Exceptions with the Internal Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–49 Nested Exceptions with an External Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–49 Handling Nonmaskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–51 Returning From Interrupt and Instruction-Related Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–51 Return Address Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–52 December 2010 Altera Corporation v Nios II Processor Reference Handbook ...
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... Advanced Debug Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16 Custom Instructions Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17 Interrupt Vector Custom Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19 Floating-Point Hardware Custom Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19 Endian Converter Custom Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20 Bitswap Custom Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20 The Quartus II IP File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–21 Nios II Processor Reference Handbook Contents December 2010 Altera Corporation ...
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... Nios II/e Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20 Arithmetic Logic Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–20 Memory Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21 Instruction Execution Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21 Instruction Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21 Exception Handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–21 JTAG Debug Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22 Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–22 December 2010 Altera Corporation vii Nios II Processor Reference Handbook ...
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... Procedure Linkage Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–19 Linux Program Interpreter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–20 Linux Initialization and Termination Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Linux Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 System Calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Userspace Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Atomic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Processor Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Development Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–21 Nios II Processor Reference Handbook Contents December 2010 Altera Corporation ...
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... Assembler Pseudo-Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–4 Assembler Macros . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5 Instruction Set Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–5 Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–104 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8–104 Additional Information How to Find Further Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–2 December 2010 Altera Corporation ix Nios II Processor Reference Handbook ...
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... Nios II Processor Reference Handbook Contents December 2010 Altera Corporation ...
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... Part Number: NII51018-10.1.0 Chapter 7. Application Binary Interface Revised: Part Number: NII51016-10.1.0 Chapter 8. Instruction Set Reference Revised: Part Number: NII51017-10.1.0 December 2010 Altera Corporation December 2010 December 2010 December 2010 December 2010 December 2010 December 2010 December 2010 December 2010 Chapter Revision Dates ...
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... Nios II Processor Reference Handbook Chapter Revision Dates December 2010 Altera Corporation ...
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... Chapter 3, Programming Model Chapter 4, Instantiating the Nios II Processor in SOPC Builder ■ f For information about the revision history for chapters in this section, refer to “Document Revision History” in each individual chapter. December 2010 Altera Corporation Section I. Nios II Processor Design ® II processor. Nios II Processor Reference Handbook ...
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... I–2 Nios II Processor Reference Handbook Section I: Nios II Processor Design December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... A Nios II processor system consists of a Nios II processor core, a set of on-chip peripherals, on-chip memory, and interfaces to off-chip memory, all implemented on a single Altera device. Like a microcontroller family, all Nios II processor systems use a consistent instruction set and programming model. Getting Started with the Nios II Processor Getting started with the Nios II processor is similar to any other microcontroller family ...
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... SRAM Memory If the prototype system adequately meets design requirements using an Altera-provided reference design, you can copy the reference design and use the final hardware platform. Otherwise, you can customize the Nios II processor system until it meets cost or performance requirements. Customizing Nios II Processor Designs In practice, most FPGA designs implement some extra logic in addition to the processor system ...
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... Extra resources can provide a few extra gates and registers as glue logic for the board design; or extra resources can implement entire systems. For example, a Nios II processor system consumes only large Altera FPGA, leaving the rest of the chip’s resources available to implement other functions. ...
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... Software development proceeds in the same manner as for traditional, nonconfigurable processors. OpenCore Plus Evaluation You can evaluate the Nios II processor without a license. With Altera's free OpenCore Plus evaluation feature, you can perform the following actions: ■ Simulate the behavior of a Nios II processor within your system December 2010 Altera Corporation 1– ...
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... October 2005 5.1.0 Maintenance release. May 2005 5.0.0 Maintenance release. Nios II Processor Reference Handbook AN 320: OpenCore Plus Evaluation chapter in volume 4 of the Quartus II Handbook page on the Altera website Changes December 2010 Altera Corporation Chapter 1: Introduction Referenced Documents ® II logic analyzer to ...
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... Chapter 1: Introduction Document Revision History Table 1–1. Document Revision History (Part Date Version September 2004 1.1 Maintenance release. May 2004 1.0 Initial release. December 2010 Altera Corporation Changes Nios II Processor Reference Handbook 1–7 ...
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... Nios II Processor Reference Handbook Chapter 1: Introduction Document Revision History December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Optional Module Module chapter of the Nios II Processor Reference Handbook. Each Chapter 2: Processor Architecture Processor Implementation Tightly Coupled Instruction Memory Tightly Coupled Instruction Memory Instruction Bus Unit Data Bus Tightly Coupled Data Memory Data Tightly Coupled Data Memory December 2010 Altera Corporation ...
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... Reference Handbook. For details about the rdprs and wrprs instructions, refer to the Instruction Set Reference The Nios II architecture allows for the future addition of floating-point registers. December 2010 Altera Corporation chapter of the Nios II Processor Reference Handbook. For complete chapter of the Nios II Processor Reference Handbook. ...
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... For further information, refer to the Nios II Processor Reference Handbook Chapter 2: Processor Architecture Table 2–1. Details Table 2–1. Programming Model Nios II Custom Instruction User Guide. December 2010 Altera Corporation Arithmetic Logic Unit ...
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... The Nios II Embedded Design Suite (EDS) provides software implementations of primitive floating-point operations other than addition, subtraction, multiplication, and division. This includes operations such as floating-point conversions and comparisons. The software implementations of these primitives are 100% compliant with IEEE 754-1985. December 2010 Altera Corporation Implementation Implemented ...
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... To add floating-point custom instructions to your Nios II processor core, refer to “Custom Instructions Page” in the chapter of the Nios II Processor Reference Handbook. The Nios II floating-point custom instructions are based on the Altera megafunctions. f For details on each individual floating-point megafunction, including acceleration factors and device resource usage, refer to the megafunction user guides, available on ...
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... With the GCC 4 compiler toolchain, precompiled libraries are compiled with double-precision floating-point constants. The behavior of precompiled floating-point library functions such as sin() and cos() is unaffected by the presence of the floating-point custom instructions. December 2010 Altera Corporation Floating-Point Custom Instructions Precision Present? No ...
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... Exception addresses are specified in SOPC Builder at system generation time. Nios II Processor Reference Handbook cpu_resettaken signal. cpu_resettaken signal for 1 cycle when the reset is Instantiating the Nios II Processor in SOPC Builder Instantiating the Nios II Processor in SOPC Builder Chapter 2: Processor Architecture Reset and Debug Signals Table 2–4. chapter of the December 2010 Altera Corporation ...
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... The PIE bit of the status register is 1 ■ An interrupt-request input, irq<n>, is asserted The corresponding bit n of the ienable register is 1 ■ December 2010 Altera Corporation Guide. For details about EIC usage, refer to “Exception Programming Model chapter of the Nios II Processor Reference 2–9 ...
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... Nios II Processor Reference Handbook. 1 The interrupt vector custom instruction is not compatible with the EIC interface. For the Nios II/f core, the EIC interface with the Altera vectored interrupt controller component provides superior performance. Table 2–5 details the implementation of the interrupt vector custom instruction. ...
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... The Nios II architecture hides the hardware details from the programmer, so programmers can develop Nios II applications without specific knowledge of the hardware implementation. f For details that affect programming issues, refer to the the Nios II Processor Reference Handbook. December 2010 Altera Corporation ® Memory-Mapped (Avalon-MM) master port Programming Model Nios II Processor Reference Handbook 2–11 ...
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... MPU Data Regions Tightly Coupled M Memory 1 Tightly Coupled M Memory N M Avalon Master Port Avalon Slave Port S for details of the Avalon-MM interface. Chapter 2: Processor Architecture Memory and I/O Organization Avalon System Interconnect Fabric S Memory Slave S Peripheral Data Data December 2010 Altera Corporation ...
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... Load and store operations can complete in a single clock cycle when the data master port is connected to zero-wait-state memory. December 2010 Altera Corporation of the system. The instruction master MAX for details. The Nios II architecture supports tightly-coupled for details. 2– ...
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... Regular memory is located off-chip, and access time is long compared to on-chip memory ■ The largest, performance-critical instruction loop is smaller than the instruction cache Nios II Processor Reference Handbook Chapter 2: Processor Architecture Memory and I/O Organization “Cache Memory” on for details. December 2010 Altera Corporation ...
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... Software can guarantee that performance-critical code or data is located in ■ tightly-coupled memory ■ No real-time caching overhead, such as loading, invalidating, or flushing memory December 2010 Altera Corporation “Tightly-Coupled Memory” on page 2–15 chapter of the Nios II Processor Reference Handbook. Nios II Processor Reference Handbook 2–15 for ...
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... Therefore, the flexible address map does not affect application developers. Memory Management Unit The optional Nios II MMU provides the following features and functionality: ■ Virtual to physical address mapping Memory protection ■ Nios II Processor Reference Handbook Chapter 2: Processor Architecture Memory and I/O Organization Using Tightly Coupled tutorial. December 2010 Altera Corporation ...
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... Amount of region memory defined by size or upper address limit ■ Read and write access permissions for data regions ■ Execute access permissions for instruction regions Overlapping regions ■ December 2010 Altera Corporation Programming Model chapter of the Nios II Processor Nios II Processor Reference Handbook 2–17 ...
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... The Nios II MMU does not support the JTAG debug module trace. The debug module connects to the JTAG circuitry in an Altera FPGA. External debugging probes can then access the processor via the standard JTAG interface on the FPGA. On the processor side, the debug module connects to signals inside the processor core ...
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... JTAG Target Connection The JTAG target connection provides the ability to connect to the processor through the standard JTAG pins on the Altera FPGA. This provides basic capabilities to start and stop the processor, and examine and edit registers and memory. The JTAG target connection is the minimum requirement for the Nios II flash programmer. ...
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... Assert a trigger signal output. This trigger output can be used, for example, to trigger an external logic analyzer. Turn on trace collection. Turn off trace collection. Store one sample of the bus to trace buffer. Enable an armed trigger. Chapter 2: Processor Architecture JTAG Debug Module “Armed 2–20. Table 2–7 lists December 2010 Altera Corporation ...
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... Load data only ■ Load address and data ■ Store address and data Address and data for both loads and stores ■ ■ Single sample of the data bus upon trigger event December 2010 Altera Corporation 2–21 Nios II Processor Reference Handbook ...
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... Nios II Processor Reference Handbook chapter of the Nios II Processor Reference Handbook chapter of the Nios II Processor chapter of the Nios II Processor Reference chapter of the Nios II Processor Reference Handbook Embedded Peripherals IP User Guide page on the Altera website Changes Chapter 2: Processor Architecture Referenced Documents December 2010 Altera Corporation ...
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... October 2005 5.1.0 Maintenance release. May 2005 5.0.0 Added tightly-coupled memory. December 2004 1.2 Added new control register ctl5. September 2004 1.1 Updates for Nios II 1.01 release. May 2004 1.0 Initial release. December 2010 Altera Corporation Changes Nios II Processor Reference Handbook 2–23 ...
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... Nios II Processor Reference Handbook Chapter 2: Processor Architecture Document Revision History December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Nios II Processor Reference Handbook for more information about the “Memory Protection Unit” on page 3–8 “Address Space and Memory Partitions” on page 3–4 for more information about MMU pages. Chapter 3: Programming Model Operating Modes for more information “Virtual December 2010 Altera Corporation ...
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... MMU-based Nios II processor. Do not include an MMU in your Nios II system unless your operating system requires it. 1 The Altera HAL and HAL-based real-time operating systems do not support the MMU. If your system needs memory protection, but not virtual memory management, refer to “ ...
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... Nios II Processor Reference Handbook Used By Memory Access Operating Bypasses TLB system Operating Bypasses TLB system Operating Uses TLB system Chapter 3: Programming Model Memory Management Unit Page Offset User Mode Default Data Access Cacheability No Disabled No Enabled No Set by TLB December 2010 Altera Corporation 0 ...
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... TLB miss) must point to low physical memory so that hardware can correctly map their virtual addresses into the kernel partition. This restriction is enforced by the Nios II Processor parameter editor in SOPC Builder. December 2010 Altera Corporation Used By Memory Access User ...
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... Nios II Processor Reference Handbook Table ® ® II, Stratix II, Stratix II GX—128 entries, requiring one M4K RAM Instantiating the Nios II Processor in SOPC Builder chapter of the Nios II Processor Reference Chapter 3: Programming Model Memory Management Unit 3–2. For partitions that are December 2010 Altera Corporation ...
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... TLB miss exception else take fast TLB miss exception December 2010 Altera Corporation Table 3–3 describes the tag portion of a TLB entry. Description VPN is the virtual page number field. This field is compared with the top 20 bits of the virtual address ...
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... Region size or upper address limit ■ ■ Access permissions ■ Default cacheability (data regions only) Nios II Processor Reference Handbook “Memory Management Unit” on page Chapter 3: Programming Model Memory Protection Unit Example 3–2. for details on TLB exceptions. 3–3. December 2010 Altera Corporation ...
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... Any instruction that performs a memory access that violates the access permissions triggers an exception. Additionally, any instruction that performs a memory access that does not match any region triggers an exception. December 2010 Altera Corporation 3–9 Nios II Processor Reference Handbook ...
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... Nios II Processor Reference Handbook for more information on cache bypass. for more information. Table 3–5. Some registers have names recognized by the Function Register r16 r17 r18 r19 Chapter 3: Programming Model Registers Name Function Callee-saved register Callee-saved register Callee-saved register Callee-saved register December 2010 Altera Corporation ...
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... All nonreserved control registers have names recognized by the assembler. Table 3–6. Control Register Names and Bits (Part Register 0 status 1 estatus 2 bstatus 3 ienable 4 ipending 5 cpuid 6 Reserved 7 exception December 2010 Altera Corporation Function Register r20 r21 r22 r23 r24 et r25 bt r26 gp r27 sp r28 fp r29 ea r30 ...
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... Table 3–23 on page 3–22 (2) Refer to Table 3–25 on page 3–23 Reserved PRS CRS Description Chapter 3: Programming Model Registers Register Contents Table 3–7 shows the layout of the Access Reset Available EIC interface and shadow Read/Write 1 register sets only (4) EIC Read 0 interface only (3) December 2010 Altera Corporation 0 ...
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... TLB miss exception is a fast TLB miss or a double TLB miss. In systems without an MMU always zero the user mode bit. When the processor operates in user mode. (2) When the processor operates in supervisor mode. In systems without U an MMU always zero. December 2010 Altera Corporation Description 3–13 Access Reset Available Shadow ...
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... Nios II Processor Reference Handbook Description Table 3–9 shows the layout of the estatus register PRS CRS “The sstatus Register” on page for more information. Chapter 3: Programming Model Registers Access Reset Available Read/Write 0 Always “External Interrupt Controller Interface” 3–27. December 2010 Altera Corporation 0 ...
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... The cpuid Register The cpuid register holds a constant value that uniquely identifies each processor in a multiprocessor system. The cpuid value is determined at system generation time and is guaranteed to be unique for each processor in the system. Writing to the cpuid register has no effect. The exception Register ...
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... Reserved Table 3– VPN Description Chapter 3: Programming Model Registers Instantiating Access Reset Available Only with extra Read 0 exception information Rsvd CAUSE shows the layout of the Rsvd Access Reset Available Only with Read/Write 0 MMU Only with Read/Write 0 MMU December 2010 Altera Corporation 0 0 ...
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... When instructions are allowed to execute the global flag. When tlbmisc.PID is included in the TLB lookup. When tlbmisc.PID is ignored and only the G virtual page number is used in the TLB lookup. PFN is the physical frame number field. All unused upper bits must PFN be zero. December 2010 Altera Corporation ...
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... D Access Reset Available Only with Read/Write 0 MMU Only with Write 0 MMU Only with Read/Write 0 MMU Only with Read/Write 0 MMU Only with Read 0 MMU Only with Read 0 MMU Only with Read 0 MMU Only with Read 0 MMU December 2010 Altera Corporation 0 ...
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... TLB has priority over the value written by the wrctl instruction. The size of the PID field is configured in SOPC Builder at system generation, and can be from bits. If system software defines a process identifier smaller than the PID field, unused upper bits must be written as zero. December 2010 Altera Corporation 3–19 Nios II Processor Reference Handbook ...
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... To see how to control the extra exception information option, refer to the the Nios II Processor in SOPC Builder Nios II Processor Reference Handbook Chapter 3: Programming Model for more information on these exceptions. chapter of the Nios II Processor Reference Handbook. December 2010 Altera Corporation Registers Instantiating ...
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... The config register configures Nios II runtime behaviors that do not need to be preserved during exception processing (in contrast to the information in the status register). Table 3–21 Table 3–21. config Control Register Fields December 2010 Altera Corporation BADDR Description shows which shows the layout of the config register. ...
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... Chapter 3: Programming Model Registers Access Reset Available Only with Read/Write 0 MPU Only with the EIC interface Read/Write 0 and shadow register sets Table 3– (1) INDEX D Access Reset Available Only with Read/Write 0 MPU Only with Read/Write 0 MPU Only with Read/Write 0 MPU December 2010 Altera Corporation 0 ...
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... When the data region is cacheable. PERM specifies the access permissions for the region. PERM December 2010 Altera Corporation Table 3–25 shows the layout of the mpuacc register with Table 3–26 shows the layout of the mpuacc register with the LIMIT field. ...
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... Chapter 3: Programming Model Registers Access Reset Available Only with Write 0 MPU Only with Write 0 MPU Region Size 64 bytes 128 bytes 256 bytes 512 bytes 128 KB 256 KB 512 December 2010 Altera Corporation ...
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... You can override the default cacheability and force an address to noncacheable with an ldio or stio instruction. 1 The bit 31 cache bypass feature is supported when the MPU is present. Refer to “Cache Memory” on page 3–53 December 2010 Altera Corporation MASK Encoding 0x1E00000 0x1C00000 0x1800000 ...
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... The WR flag always returns Chapter 3: Programming Model Registers Table 3–29 shows possible Table 3–30 shows possible values User Permissions None None Execute User Permissions None None Read None Read Read/Write “MPU Region Read “MPU Region Read December 2010 Altera Corporation ...
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... SRS is the switched register set bit. The processor sets SRS to 1 when an external interrupt occurs, if the interrupt required the processor to SRS switch to a different register set. RSIE NMI PRS December 2010 Altera Corporation “Exception Processing” on page shows the layout of the sstatus register ...
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... Nios II Processor Reference Handbook Description (1) (1) (1) (1) (1) (1) “Requested Register Set” on page Table 3–35 on page 3–46. Chapter 3: Programming Model Registers Access Reset Available Read/Write Undefined (1) Read/Write Undefined (1) Read/Write Undefined (1) Read/Write Undefined (1) Read/Write Undefined (1) Read/Write Undefined (1) 3–37. For details December 2010 Altera Corporation ...
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... Execute a wrctl instruction to the mpuacc register with the mpuacc.WR field set to one and the mpuacc.RD field cleared to zero. The MPU region write operation sets the values for mpubase.BASE, mpuacc.MASK or mpuacc.LIMIT, mpuacc.C, and mpuacc.PERM as the new attributes for the MPU region. December 2010 Altera Corporation 3–29 Nios II Processor Reference Handbook ...
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... The MPU is disabled on system reset. Before enabling the MPU, Altera recommends initializing all MPU regions. Enable desired instruction and data regions by writing each region’s attributes to the mpubase and mpuacc registers as described in Region Read and Write Operations” ...
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... Internal interrupt controller—the nonvectored interrupt controller that is integral to the Nios II processor. The internal interrupt controller is available in all revisions of the Nios II processor. Vectored interrupt controller (VIC)—an Altera-provided external interrupt ■ controller. ■ Exception (interrupt) latency—The time elapsed between the event that causes the exception (assertion of an interrupt request) and the execution of the first instruction at the handler address ...
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... Chapter 3: Programming Model Exception Processing Vector Reset Break Reset General exception Requested handler address (3) Requested handler address (3) General exception Fast TLB Miss exception General exception General exception General exception General exception General exception General exception General exception Break December 2010 Altera Corporation ...
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... The worst-case interrupt latency for interrupt i is determined by that interrupt’s maximum masked time the maximum disabled time, whichever is greater. Reset Exceptions When a processor reset signal is asserted, the Nios II processor performs the following steps: December 2010 Altera Corporation Available Cause Address badaddr (data MMU ...
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... A break can occur during exception processing, enabling debug tools to debug exception handlers. Nios II Processor Reference Handbook Chapter 3: Programming Model Exception Processing Nios II Custom Instruction User Guide December 2010 Altera Corporation for reset ...
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... Interrupt Exceptions A peripheral device can request an interrupt by asserting an interrupt request (IRQ) signal. IRQs interface to the Nios II processor through an interrupt controller. You can configure the Nios II processor with either of the following interrupt controller options: December 2010 Altera Corporation 3–35 Nios II Processor Reference Handbook ...
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... RIL is greater than status.IL. The RIL is ignored for nonmaskable interrupts. Nios II Processor Reference Handbook Chapter 3: Programming Model Guide. “Requested Handler Address” “Requested Interrupt Level” “Requested Register Set” “Requested NMI December 2010 Altera Corporation Exception Processing ...
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... Less-critical interrupts can share register sets, provided the ISRs are protected from register corruption as noted in The method for mapping interrupts to register sets is specific to the particular EIC implementation. December 2010 Altera Corporation 3–37 “Requested Register Set”. Nios II Processor Reference Handbook ...
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... Figure 3–2. Relationship Between ienable, ipending, PIE and Hardware Interrupts External hardware interrupt request inputs irq[31..0] Nios II Processor Reference Handbook “Exception Processing Flow” on Figure 3–2 shows the relationship 31 ienable Register . . . 31 ipending Register . . . . . . PIE bit Generate Hardware Interrupt Chapter 3: Programming Model Exception Processing 0 0 December 2010 Altera Corporation ...
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... If the instruction is not implemented in hardware, control is passed to an exception routine that might choose to emulate the instruction in software. For more information, refer to Unimplemented Instructions” on page December 2010 Altera Corporation “Exception Processing Flow” 3–34. 3–60. ...
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... Nios II Processor Reference Handbook Instantiating the Nios II Processor in SOPC chapter of the Nios II Processor Reference Handbook to see the Nios II Core Implementation Details “Operating Modes” on page 3–1 Table 3–2 on page Chapter 3: Programming Model Exception Processing for more information. 3–4. December 2010 Altera Corporation ...
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... The two cases are divide by zero and a signed division that divides the largest negative number -2147483648 (0x80000000 (0xffffffff). Division error detection is only available if divide instructions are supported by hardware. December 2010 Altera Corporation Instantiating the Nios II Processor in SOPC Instantiating the Nios II Processor in SOPC Instantiating the Nios II Processor in SOPC Nios II Processor Reference Handbook 3– ...
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... TLB permission violation (execute)—Any instruction fetch can cause this exception. ■ TLB permission violation (read)—Any load instruction can cause this exception. TLB permission violation (write)—Any store instruction can cause this exception. ■ Nios II Processor Reference Handbook Chapter 3: Programming Model Exception Processing December 2010 Altera Corporation ...
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... For a detailed discussion of writing programs to take advantage of exception and interrupt handling, refer to the Developer’s Handbook. December 2010 Altera Corporation “Processing a Break” on page Exception Handling chapter of the Nios II Software Nios II Processor Reference Handbook 3–43 ...
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... Nios II Processor Reference Handbook Chapter 3: Programming Model Exception Processing chapter of the Nios II Processor Reference December 2010 Altera Corporation ...
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... Interrupts can be re-enabled by writing one to the PIE bit, thereby allowing the current ISR to be interrupted. Typically, the exception routine adjusts ienable so that IRQs of equal or lower priority are disabled before re-enabling interrupts. Refer to “Handling Nested Exceptions” on page 3–48 December 2010 Altera Corporation RNMI == 0 status.PIE == 1 RIL <= RIL > ...
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... Exception Processing status.EH==0 TLB Miss No TLB Miss (4) TLB No TLB Permission Permission Violation Violation (4) VPN (6) No change No change Fast TLB exception General exception vector vector (3) (9) No change (7) status return address (14) (15) (16) (17) 0 (19) 1 (20) No change No change No change No change No change December 2010 Altera Corporation ...
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... To determine the cause of an exception, simply read the cause of the exception from exception.CAUSE and then transfer control to the appropriate exception routine. 1 Extra exception information is always enabled in Nios II systems containing an MMU or MPU. December 2010 Altera Corporation “The exception Register” on page “The badaddr Register” on page for more information. 3–47 3– ...
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... When you have not included the extra exception information in your Nios II system, your exception handler must determine the cause of exception itself. For this reason, Altera recommends always enabling the extra exception information. When the extra exception information is not available, use the sequence in Example 3– ...
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... Each interrupt is assigned to a dedicated shadow register set ■ All interrupts with the same RIL are assigned to dedicated shadow register sets. December 2010 Altera Corporation 3–43. For details about unimplemented instructions, refer chapter of the Nios II Processor Reference Handbook. For “Instruction-Related Exceptions” on Nios II Processor Reference Handbook 3– ...
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... Table 3–37 illustrate the validity of register set assignments when Register Set 1 IRQ0 IRQ1 IRQ3 Register Set 1 IRQ0 IRQ1 IRQ3 Chapter 3: Programming Model Exception Processing Register Set 2 IRQ2 IRQ4 IRQ5 IRQ6 Register Set 2 IRQ2 IRQ4 IRQ5 IRQ6 December 2010 Altera Corporation ...
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... It is not necessary to save and restore the exception temporary (et or r24) register. When executing the eret instruction, the processor performs the following tasks: December 2010 Altera Corporation 3–49. “Nested Exceptions with an External Nios II Processor Reference Handbook ...
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... Masking Interrupts with an External Interrupt Controller Masking Individual Interrupts Typical EIC implementations allow system software to mask individual interrupts. The method of masking individual interrupts is implementation-specific. Nios II Processor Reference Handbook Chapter 3: Programming Model Exception Processing December 2010 Altera Corporation ...
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... Instructions are provided to initialize the cache, flush the caches whenever necessary, and to bypass the data cache to properly access memory-mapped peripherals. The Nios II architecture provides the following mechanisms to bypass the cache: December 2010 Altera Corporation for more information. for more information. Nios II Core Implementation Details 3– ...
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... Organization” on page chapter of the Nios II Processor Reference chapter of the Nios II Processor Reference Handbook for details of for more information. Chapter 3: Programming Model Memory and Peripheral Access “Address Space and 3–6. Cache and Tightly Coupled Processor December 2010 Altera Corporation ...
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... These operations load/store byte and half-word data from/to peripherals without caching or buffering. ldhio ldhuio sthio December 2010 Altera Corporation Description Table 3–39 support byte and half-word transfers. Description Nios II Processor Reference Handbook 3–55 ...
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... Use movia to load a movui register with an address. movia Nios II Processor Reference Handbook Chapter 3: Programming Model Instruction Set Categories Description Table 3–41. Description December 2010 Altera Corporation ...
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... December 2010 Altera Corporation Table Description Description Nios II Processor Reference Handbook 3–57 3– ...
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... Nios II Processor Reference Handbook Table 3–44. These instructions do not have delay slots. Description Table 3–45. The conditional branches support the following Description “Comparison Instructions” on page 3–57 Chapter 3: Programming Model Instruction Set Categories for a description of the December 2010 Altera Corporation ...
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... Machine-generated C functions and assembly language macros provide access to custom instructions, and hide implementation details from the user. Therefore, most software developers never use the custom assembly language instruction directly. No-operation Instruction The Nios II assembler provides a no-operation instruction, nop. December 2010 Altera Corporation Description Guide. 3–59 Processor ...
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... Nios II Processor Reference Handbook chapter of the Nios II Processor chapter of the Nios II Processor Reference chapter of the Nios II Software Developer’s Handbook chapter of the Nios II Software Developer’s Embedded Peripherals IP User Guide Chapter 3: Programming Model Referenced Documents December 2010 Altera Corporation ...
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... Maintenance release. Added details for new control register ctl5. ■ September 2004 1.1 Updated details of debug and break processing to reflect new behavior of the break ■ instruction. May 2004 1.0 Initial release. December 2010 Altera Corporation Changes Nios II Processor Reference Handbook 3–61 ...
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... Nios II Processor Reference Handbook Chapter 3: Programming Model Document Revision History December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... The main purpose of the Core Nios II page is to select the processor core. The core you select on this page affects other options available on this and other pages. Altera offers the following Nios II cores: ■ Nios II/f—The Nios II/f “fast” core is designed for fast performance result, this core presents the most configuration options allowing you to fine-tune the processor for performance ...
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... Offset box. This address, displayed next to the Offset box, is always a physical address, even when an MMU is present. December 2010 Altera Corporation Figure 4–1, the Core Nios II page displays a “selector guide” table that ...
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... Do not include an MMU in your Nios II system unless your operating system requires it. The MMU is only useful with software that takes advantage of it. Many Nios II systems involve simpler system software, such as Altera Such software is unlikely to function correctly with an MMU-based Nios II processor. Fast TLB Miss Exception Vector The fast TLB miss exception vector is a special exception vector used exclusively by the MMU to handle TLB miss exceptions ...
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... DRAM, and disable bursts when instructions are stored in SRAM. Bursting to DRAM typically improves memory bandwidth, but might consume additional FPGA resources. Be aware that when bursts are enabled, accesses to December 2010 Altera Corporation Programming Model chapter of the Nios II Programming Model chapter of the Nios II Figure 4– ...
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... For example, with a 32-byte cache line, transferring control to address 8 results in a burst with the following address sequence: 8, 12, 16, 20, 24, 28 Nios II Processor Reference Handbook Chapter 4: Instantiating the Nios II Processor in SOPC Builder . MAX Caches and Memory Interfaces Page December 2010 Altera Corporation ...
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... Omit data master port—If you set Data Cache to None, you can optionally ■ turn on Omit data master port to remove the Avalon-MM data master port from the Nios II processor. In this case, you must include a tightly-coupled data memory. December 2010 Altera Corporation 4–7 Nios II Processor Reference Handbook ...
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... Nios II processor in the SOPC Builder System Contents tab. You must connect each port to exactly one memory component in the system. Nios II Processor Reference Handbook Chapter 4: Instantiating the Nios II Processor in SOPC Builder . MAX Caches and Memory Interfaces Page December 2010 Altera Corporation ...
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... Nios II processor without resetting the entire SOPC Builder system. The signals are exported to the top level of your SOPC Builder system. f For further details on the reset signals, refer to the Nios II Processor Reference Handbook. December 2010 Altera Corporation shows the Advanced Features page. Processor Architecture 4–9 chapter of the ...
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... Misaligned memory access—Misaligned memory access detection is only available for the Nios II/f core. When Misaligned memory access is on, the processor checks for misaligned memory accesses. Nios II Processor Reference Handbook Chapter 4: Instantiating the Nios II Processor in SOPC Builder Advanced Features Page December 2010 Altera Corporation ...
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... For details about the EIC controller, refer to “Exception Processing” in the Programming Model December 2010 Altera Corporation chapter of the Nios II Processor Reference Handbook. chapter of the Nios II Processor Reference Handbook. 4–11 Nios II Processor Reference Handbook ...
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... Figure 4–4. MMU and MPU Settings Page in the Nios II Processor Parameter Editor Nios II Processor Reference Handbook Chapter 4: Instantiating the Nios II Processor in SOPC Builder shows the MMU and MPU Settings page. MMU and MPU Settings Page Programming Model December 2010 Altera Corporation ...
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... The maximum region size is the size of the Nios II instruction and data addresses automatically determined when the Nios II system is generated in SOPC Builder. Maximum region size is based on the address range of slaves connected to the Nios II instruction and data masters. December 2010 Altera Corporation Programming Model chapter of the Nios II Processor chapter of the Nios II Processor Reference Handbook. ...
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... Table 4–1. Debug Configuration Features Feature Connects to the processor through the standard JTAG pins on the Altera FPGA. This provides the JTAG Target Connection basic capabilities to start and stop the processor, and examine/edit registers and memory. ...
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... Lauterbach GmbH website (www.lauterbach.com). Table 4–2. JTAG Debug Module Levels (Part Debug Feature No Debug Logic Usage On-Chip Memory Usage December 2010 Altera Corporation Level 1 Level 2 0 300—400 LEs 800—900 LEs 2,400—2,700 LEs 3,100—3,700 LEs ...
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... Table 4–2: (1) Level 4 requires the purchase of a software upgrade from FS2 or Lauterbach. (2) Not including the dedicated JTAG pins on the Altera FPGA. (3) An additional license from FS2 is required to use more than 16 frames. (4) Off-chip trace requires the purchase of additional hardware from FS2 or Lauterbach. ...
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... To display custom instructions in the table of active components on the SOPC Builder System Contents tab, click Filter in the lower right of the System Contents tab, and turn on Nios Custom Instruction. December 2010 Altera Corporation Processor Architecture chapter of the Nios II Processor Reference Handbook 4–17 ...
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... For full details on the topic of custom instructions, including working example designs, refer to the Instruction User The following sections describe the default custom instructions Altera provides. Nios II Processor Reference Handbook Chapter 4: Instantiating the Nios II Processor in SOPC Builder Guide ...
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... The interrupt vector custom instruction is not compatible with the EIC interface. For the Nios II/f core, the EIC interface with the Altera vectored interrupt controller component provides superior performance. f For details of the interrupt vector custom instruction implementation, refer to “ ...
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... Bitswap Custom Instruction The Nios II processor core offers a bitswap custom instruction to reduce the time spent performing bit reversal operations. Nios II Processor Reference Handbook Chapter 4: Instantiating the Nios II Processor in SOPC Builder Custom Instructions Page Processor December 2010 Altera Corporation ...
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... May 2008 8.0.0 Added exception handling options Advanced Features page. ■ December 2010 Altera Corporation Guide file (.qip file generated by the MegaWizard™ Plug-in chapter of the Nios II Processor Reference chapter of the Nios II Processor Reference Handbook chapter of the Nios II Processor Reference Handbook Changes 4– ...
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... Table 4–3. Document Revision History (Part Date Version October 2007 7.2.0 Changed title to match other Altera documentation. Revised to reflect new MegaWizard interface. ■ Added ■ Instruction” on page May 2007 7.1.0 Added table of contents to Introduction section. ■ Added Referenced Documents section. ...
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... Chapter 7, Application Binary Interface Chapter 8, Instruction Set Reference ■ f For information about the revision history for chapters in this section, refer to “Document Revision History” in each individual chapter. December 2010 Altera Corporation Section II. Nios II Processor Implementation and Reference ® II processor. Nios II Processor Reference Handbook ...
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... II–2 Nios II Processor Reference Handbook Section II: Nios II Processor Implementation and Reference December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Introduction Nios II without MMU 4 GB with MMU 512 bytes Yes Dynamic Optional 512 bytes – I/O instructions ■ Bit-31 cache bypass ■ Optional MMU ■ Optional 1-cycle (3) Optional 1-cycle barrel shifter (3) Optional Optional Optional Optional Optional December 2010 Altera Corporation ...
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... For details, refer to the arithmetic logic unit description for each core. Device Family Support All Nios II cores provide the same support for target Altera cores provide device family support to each of the Altera device families as shown in Table 5–2. ...
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... The Nios II/f fast core is designed for high execution performance. Performance is gained at the expense of core size. The base Nios II/f core, without the memory management unit (MMU) or memory protection unit (MPU), is approximately 25% larger than the Nios II/s core. Altera designed the Nios II/f core with the following design goals in mind: ■ ...
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... DSP Block—Includes DSP block multipliers available on the target device. This option is available only on Altera FPGAs that have DSP Blocks. ■ Embedded Multipliers—Includes dedicated embedded multipliers available on the target device. This option is available only on Altera FPGAs that have embedded multipliers. Logic Elements—Includes hardware multipliers built from logic element (LE) ■ ...
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... Result Latency Instruction Cycles – – – 100 (Depends on result of mul dependency on previous results ; No dependency on previous results ; 100 (Depends on result of mul) December 2010 Altera Corporation Nios II/f Core Supported Instructions None mul, muli mul, muli, mulxss, mulxsu, mulxuu mul, muli div, divu ...
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... Both the instruction and data cache addresses are divided into fields based on whether or not an MMU is present in your system. address fields for systems without an MMU present. Table 5–5. Cache Byte Address Fields tag December 2010 Altera Corporation line Table 5–10 on ® Memory-Mapped (Avalon-MM) Table 5– ...
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... Write-allocate (i.e store instruction, a cache miss allocates the line for that address) Virtually-indexed, physically-tagged, when MMU present ■ Nios II Processor Reference Handbook shows the cache physical byte address fields for systems with line Chapter 5: Nios II Core Implementation Details Nios II/f Core offset offset December 2010 Altera Corporation 0 0 ...
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... When the data cache is enabled, you can enable bursting on the data master port. Consult the documentation for memory devices connected to the data master port to determine whether bursting can improve performance. December 2010 Altera Corporation Table 5–9 Ignore Tag Field Consider Tag Field ...
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... The Nios II/f core provides options to improve the performance of the Nios II MPU. For details on the MPU architecture, refer to the Nios II Processor Reference Handbook. Nios II Processor Reference Handbook Chapter 5: Nios II Core Implementation Details Nios II/f Core Programming Model chapter of the Programming Model chapter of the December 2010 Altera Corporation ...
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... An A-stage divide instruction is still performing its operation. This only occurs ■ when the optional divide circuitry is available. ■ An A-stage multi-cycle custom instruction is asserting its stall signal. This only occurs if the design includes multi-cycle custom instructions. December 2010 Altera Corporation 5–11 Stage Name Fetch Decode Execute ...
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... Chapter 5: Nios II Core Implementation Details Nios II/f Core Table 5–10. Cycles Penalties 1 1 > 1 Late result Pipeline flush (2) Pipeline flush Late result 1 Late result > 1 Late result 1 > > (1) Late result (1) Late result 1 Late result 2 Late result December 2010 Altera Corporation ...
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... The EIC interface is an Avalon-ST sink with the following input signals: ■ eic_port_valid ■ eic_port_data Signals are rising-edge triggered, and synchronized with the Nios II clock input. December 2010 Altera Corporation Instruction Table 5–4 on page 5–6 for details. 5–13 Cycles Penalties 1— ...
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... The Nios II/s standard core is designed for small core size. On-chip logic and memory resources are conserved at the expense of execution performance. The Nios II/s core uses approximately 20% less logic than the Nios II/f core, but execution performance also drops by roughly 40%. Altera designed the Nios II/s core with the following design goals in mind: ■ ...
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... Altera FPGAs that have DSP Blocks. ■ Embedded Multipliers—Includes dedicated embedded multipliers available on the target device. This option is available only on Altera FPGAs that have embedded multipliers. ■ Logic Elements—Includes hardware multipliers built from logic element (LE) resources. None— ...
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... The data master port on the Nios II/s core is always present. Nios II Processor Reference Handbook Cycles per Hardware Details instruction – – 66 Chapter 5: Nios II Core Implementation Details Nios II/s Core Supported Instructions None mul, muli mul, muli, mulxss, mulxsu, mulxuu mul, muli div, divu Table 5–15 on Processor December 2010 Altera Corporation ...
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... Execution Pipeline This section provides an overview of the pipeline behavior for the benefit of performance-critical applications. Designers can use this information to minimize unnecessary processor stalling. Most application programmers never need to analyze the performance of individual instructions. December 2010 Altera Corporation ...
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... Branch Prediction The Nios II/s core performs static branch prediction to minimize the cycle penalty associated with taken branches. Nios II Processor Reference Handbook Chapter 5: Nios II Core Implementation Details Nios II/s Core Stage Name Fetch Decode Execute Memory Writeback December 2010 Altera Corporation ...
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... Depends on the hardware multiply or divide option. Refer to Exception Handling The Nios II/s core supports the following exception types: ■ Internal hardware interrupt Software trap ■ ■ Illegal instruction ■ Unimplemented instruction December 2010 Altera Corporation Table Instruction Table 5–12 on page 5–16 5–19 5–15. Cycles Penalties 1 1 > 1 ...
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... Nios II/e Core The Nios II/e economy core is designed to achieve the smallest possible core size. Altera designed the Nios II/e core with a singular design goal: reduce resource utilization any way possible, while still maintaining compatibility with the Nios II instruction set architecture. Hardware resources are conserved at the expense of execution performance ...
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... Shift, rotate All other instructions Combinatorial custom instructions Multi-cycle custom instructions Exception Handling The Nios II/e core supports the following exception types: December 2010 Altera Corporation Instruction Duration of Avalon-MM read transfer 9 + Duration of Avalon-MM read transfer 10 + Duration of Avalon-MM read transfer ...
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... Corrected cycle counts for shift/rotate operations. Nios II Processor Reference Handbook Chapter 5: Nios II Core Implementation Details chapter of the Nios II Processor Reference Handbook chapter of the Nios II Processor Reference Handbook chapter of the Nios II Processor Reference Handbook Embedded Peripherals IP User Guide Changes Referenced Documents December 2010 Altera Corporation ...
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... Date Version December 2004 1.2 Updates to Multiply and Divide Performance section for Nios II/f and Nios II/s cores. September 2004 1.1 Updates for Nios II 1.01 release. May 2004 1.0 Initial release. December 2010 Altera Corporation Changes Nios II Processor Reference Handbook 5–23 ...
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... Nios II Processor Reference Handbook Chapter 5: Nios II Core Implementation Details Document Revision History December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Nios II cores. A change in the architecture mandates a revision to all Nios II cores to accommodate the new architectural enhancement. For example, when Altera adds a new instruction to the instruction set, Altera consequently must update all Nios II cores to recognize the new instruction. lists revisions to the Nios II architecture. ...
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... December 2010 10.0 July 2010 9.1 November 2009 9.0 March 2009 8.1 November 2008 December 2010 Altera Corporation Notes No changes. No changes. Added an optional MMU. ■ Added an optional MPU. ■ Added advanced exception checking to detect division errors, illegal ■ instructions, misaligned memory accesses, and provide extra exception information ...
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... Added cpuid control register. ■ Bug Fix: ■ Interrupts that were disabled by wrctl ienable remained enabled for one clock cycle following the wrctl instruction. Now the instruction following such a wrctl cannot be interrupted. Chapter 6: Nios II Processor Revision History Core Revisions December 2010 Altera Corporation ...
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... May 2006 5.1 October 2005 5.0 May 2005 December 2010 Altera Corporation Bug Fixes: ■ (1) When a store to memory is followed immediately in the pipeline by a load from the same memory location, and the memory location is held in the data cache, the load may return invalid data. This situation can occur in C code compiled with optimization off (-O0) ...
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... Added cpuid control register. ■ Bug fix: The SOPC Builder top-level system module included an extra, unnecessary output port for systems with very small address spaces. Initial release of the Nios II/s core. Notes Chapter 6: Nios II Processor Revision History Core Revisions December 2010 Altera Corporation ...
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... November 2006 6.0 May 2006 5.1 October 2005 5.0 May 2005 1.1 December 2004 1.01 September 2004 1.0 May 2004 December 2010 Altera Corporation Notes No changes. No changes. No changes. No changes. No changes. No changes. No changes. No changes. No changes. No changes. No changes. No changes. Support for HardCopy devices (previous versions of the JTAG debug module did not support HardCopy devices) ...
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... Updates for Nios II cores version 5.1. May 2005 5.0.0 Updates for Nios II cores version 5.0. September 2004 1.1 Updates for Nios II cores version 1.1. May 2004 1.0 Initial release. Nios II Processor Reference Handbook Chapter 6: Nios II Processor Revision History Referenced Documents Changes December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... Return value (most-significant 32 bits) v Register arguments (first 32 bits) v Register arguments (second 32 bits) v Register arguments (third 32 bits) v Register arguments (fourth 32 bits Caller-saved general-purpose registers Callee-saved general-purpose registers (2) v (3) Exception temporary Chapter 7: Application Binary Interface Memory Alignment Normal Usage December 2010 Altera Corporation ...
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... Stacks The stack grows downward (i.e. towards lower addresses). The stack pointer points to the last used slot. The frame pointer points to the saved frame pointer near the top of the stack frame. December 2010 Altera Corporation Used by Callee Compiler Saved ...
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... Allocated and freed by a() stack (i.e. the calling function) arguments Return address Saved frame pointer Frame pointer Other saved registers Space for stack Allocated and freed by b() temporaries (i.e. the current function) Space for outgoing stack arguments Stack pointer Stacks December 2010 Altera Corporation ...
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... Stack Frame for a Function with Variable Arguments Functions that take variable arguments (varargs) still have their first 16 bytes of arguments arriving in registers r4 through r7, just like other functions. December 2010 Altera Corporation Figure 7–2 depicts what the frame looks like after alloca() is Before ...
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... Frame pointer Other saved registers Allocated and freed by b() (i.e. the current function) Space for stack temporaries Space for outgoing stack arguments Stack pointer Figure 7–3. 7–2. A function prologue is required to save a Chapter 7: Application Binary Interface Stacks 7–3. December 2010 Altera Corporation ...
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... Arguments and Return Values This section discusses the details of passing arguments to functions and returning values from functions. December 2010 Altera Corporation shows a function prologue. /* make a 16-byte frame */ /* store the return address */ /* store the frame pointer*/ ...
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... In Example 7–2, if the result type is no larger than 8 bytes, b() returns its result in r2 and r3. Nios II Processor Reference Handbook Chapter 7: Application Binary Interface Arguments and Return Values “Stack Frame for a Function 7–5. December 2010 Altera Corporation ...
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... Nios II relocation type. The bit mask specifies where the address is found in the instruction. Table 7–4. Nios II Relocation Calculation (Part Name Value R_NIOS2_NONE 0 R_NIOS2_S16 1 R_NIOS2_U16 2 R_NIOS2_PCREL16 3 R_NIOS2_CALL26 4 December 2010 Altera Corporation Example 7–3 Example 7–2. Value ELFCLASS32 ELFDATA2LSB EM_ALTERA_NIOS2 == 113 Overflow Relocated Address check (1) R (2) n/a ...
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... Bit Mask Bit Shift M B 0x000007C0 6 0x07C00000 22 0x00000FC0 6 0x00003FC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0xFFFFFFFF 0 0x0000FFFF 0 0x000000FF 0 0x003FFFC0 6 n/a n/a n/a n/a 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 n/a n/a 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0x003FFFC0 6 0xFFFFFFFF 0 0xFFFFFFFF 0 December 2010 Altera Corporation ...
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... M is the bit mask shown in ■ ■ the original instruction ■ the relocated instruction ABI for Linux Systems This section describes details specific to Linux systems beyond the Linux-specific information in December 2010 Altera Corporation Overflow Relocated Address check (1) R (2) Refer to “Thread-Local Storage” page 7– ...
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... R_NIOS2_PCREL_HA R_NIOS2_TLS_GD16 R_NIOS2_TLS_LDM16 R_NIOS2_TLS_LDO16 R_NIOS2_TLS_IE16 R_NIOS2_TLS_LE16 R_NIOS2_TLS_DTPREL R_NIOS2_GOTOFF Nios II Processor Reference Handbook Chapter 7: Application Binary Interface Table Table 7–6. Operator %got %call %gotoff_hiadj %gotoff_lo %hiadj %lo %tls_gd %tls_ldm %tls_ldo %tls_ie %tls_le %tls_ldo %gotoff ABI for Linux Systems 7–5. December 2010 Altera Corporation ...
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... Address the general dynamic model, a two-word GOT slot is allocated for x, as shown in Example 7–5. Example 7–5. GOT Slot for General Dynamic Model GOT[n] GOT[n+1] December 2010 Altera Corporation 7–19. shows the general dynamic model. # R_NIOS2_TLS_GD16 x # R_NIOS2_CALL26 __tls_get_addr R_NIOS2_TLS_DTPMOD x R_NIOS2_TLS_DTPREL x 7–13 ...
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... R_NIOS2_TLS_LDM16 x # R_NIOS2_CALL26 __tls_get_addr # R_NIOS2_TLS_LDO16 x # R_NIOS2_TLS_LDO16 x2 R_NIOS2_TLS_DTPMOD x 0 shows the initial exec model. # R_NIOS2_TLS_IE16 x R_NIOS2_TLS_TPREL x shows the local exec model. # R_NIOS2_TLS_LE16 x 7–11. # DW_OP_addr # R_NIOS2_TLS_DTPREL x # DW_OP_GNU_push_tls_address Chapter 7: Application Binary Interface ABI for Linux Systems December 2010 Altera Corporation ...
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... Table 7–7. Signals for Unhandled Intruction-Related Exceptions Supervisor-only Instruction Address TLB Permission Violation (execute) Supervisor-only Instruction Unimplemented Instruction Illegal Instruction Break Instruction Supervisor-only Data Address Misaligned Data Address Misaligned Destination Address Division Error December 2010 Altera Corporation 7–7. Exception Signal SIGSEGV SIGSEGV SIGILL SIGILL SIGILL SIGTRAP SIGSEGV ...
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... SIGSEGV SIGSEGV 7–21. Start Address High addresses × argc × argc Low addresses Chapter 7: Application Binary Interface ABI for Linux Systems Table 7–8 shows the Length Varies 4 bytes 8 bytes each 4 bytes 4 bytes each 4 bytes 4 bytes each 4 bytes December 2010 Altera Corporation ...
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... GOT entry is placed in the PLT GOT for lazy binding, as shown in For information about the PLT, refer to Example 7–15. GOT entry in PLT GOT ldw r3, %call(fun)(r22) callr r3 PLTGOT[n] December 2010 Altera Corporation # R_NIOS2_PCREL_HA _gp_got # R_NIOS2_PCREL_LO _gp_got - 4 # R_NIOS2_GOT16 R_NIOS2_GLOB_DAT x # R_NIOS2_GOT16 R_NIOS2_RELATIVE +x Example “ ...
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... Function addresses use the same SHN_UNDEF and st_value convention for PLT entries as in other architectures, such as x86_64. Nios II Processor Reference Handbook Chapter 7: Application Binary Interface Example # R_NIOS2_GOTOFF_HA x # R_NIOS2_GOTOFF_LO x Example 7–17. # R_NIOS2_GOTOFF_HA Ltable # r3 == &Ltable # r3 == Ltable[index] # Convert offset into destination 7–19. December 2010 Altera Corporation ABI for Linux Systems 7–16. ...
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... The link editor arranges for the Nth PLT entry to point to the Nth branch, res_N – res_0 is four times the index into the .rela.plt section for the corresonding R_JUMP_SLOT relocation. December 2010 Altera Corporation Example 7–18. shows the PLT entry when the PLT GOT is close enough to the small shows the initial PLT entry. 7– ...
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... Linux Program Interpreter The program interpreter is /lib/ld.so.1. Nios II Processor Reference Handbook shows the initial PLT entry. Chapter 7: Application Binary Interface ABI for Linux Systems Example 7–23. December 2010 Altera Corporation ...
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... Development Environment The following symbols are defined: ■ __nios2 ■ __nios2__ ■ __NIOS2 ■ __NIOS2__ Referenced Documents This chapter references the following document: the Nios II Processor Reference Handbook. December 2010 Altera Corporation 7–21 Programming Model chapter of the Nios II Processor Reference Handbook ...
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... May 2006 6.0.0 Maintenance release. October 2005 5.1.0 Maintenance release. May 2005 5.0.0 Maintenance release. September 2004 1.1 Maintenance release. May 2004 1.0 Initial release. Nios II Processor Reference Handbook Chapter 7: Application Binary Interface Document Revision History Changes December 2010 Altera Corporation ...
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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ...
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... A 26-bit immediate data field J-type instructions, such as call and jmpi, transfer execution anywhere within a 256-MB range. Table 8–3 shows the J-type instruction format. Table 8–3. J-Type Instruction Format Nios II Processor Reference Handbook OPX IMM26 Chapter 8: Instruction Set Reference Word Formats December 2010 Altera Corporation 0 0 ...
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... December 2010 Altera Corporation and Table 8–2. Most values of OP are encodings for I-type Instruction OP Instruction cmplti 0x20 cmpeqi 0x21 0x22 initda 0x23 ldbuio ori ...
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... IMMED addi, rB, r0, IMMED orhi rB, r0, %hiadj(label) addi, rB, r0, %lo(label) ori rB, r0, IMMED add r0, r0, r0 addi rB, rA, (-IMMED) Chapter 8: Instruction Set Reference Assembler Pseudo-Instructions OPX Instruction 0x3E 0x3F Equivalent Instruction December 2010 Altera Corporation ...
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... IMMED ..m 0xNNMM σ (X) X >> << & Y December 2010 Altera Corporation Table 8–4 lists the available macros. These macros return Description immed32 & 0xFFFF (immed32 >> 16) & 0xFFFF ((immed32 >> 16) & 0xFFFF) + ((immed32 >> 15) & 0x1) immed32 –_gp (1) Meaning X is written with Y The program counter (PC) is written with address X ...
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... The word located in data memory at byte address X An address label specified in the assembly file The value of rX treated as a signed number The value of rX treated as an unsigned number Chapter 8: Instruction Set Reference Instruction Set Reference Programming Model chapter December 2010 Altera Corporation ...
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... C = Register index of operand December 2010 Altera Corporation # The original add operation # rD is written with the carry bit # The original add operation # Branch if carry generated # The original add operation # Compare signs of sum and rA # Compare signs of sum and rB # Combine comparisons # Branch if overflow occurred ...
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... The original add operation # Branch if carry generated # The original add operation # Compare signs of sum and rA # Compare signs of sum and IMM16 # Combine comparisons # Branch if overflow occurred IMM16 Chapter 8: Instruction Set Reference Instruction Set Reference add immediate 0x04 December 2010 Altera Corporation 0 ...
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... Example: and r6, r7, r8 Calculates the bitwise logical AND of rA and rB and stores the result in rC. Description: None Exceptions: R Instruction Type Register index of operand Register index of operand rB Instruction Fields Register index of operand December 2010 Altera Corporation 0x0e 8–9 bitwise logical and ...
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... None Exceptions: I Instruction Type Register index of operand Register index of operand rB Instruction Fields: IMM16 = 16-bit unsigned immediate value Nios II Processor Reference Handbook bitwise logical and immediate into high halfword IMM16 Chapter 8: Instruction Set Reference Instruction Set Reference 0x2c December 2010 Altera Corporation 0 ...
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... Calculates the bitwise logical AND of rA and (0x0000 : IMM16) and stores the result in rB. Description: None Exceptions: I Instruction Type Register index of operand Register index of operand rB Instruction Fields: IMM16 = 16-bit unsigned immediate value December 2010 Altera Corporation IMM16 8–11 bitwise logical and immediate ...
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... Misaligned destination address Exceptions: I Instruction Type Register index of operand Register index of operand rB Instruction Fields: IMM16 = 16-bit signed immediate value Nios II Processor Reference Handbook IMM16 Chapter 8: Instruction Set Reference Instruction Set Reference branch if equal 0x26 December 2010 Altera Corporation 0 ...
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... The two least-significant bits of IMM16 are always zero, because instruction addresses must be word-aligned. Misaligned destination address Exceptions: I Instruction Type Register index of operand Register index of operand rB Instruction Fields: IMM16 = 16-bit signed immediate value December 2010 Altera Corporation branch if greater than or equal signed IMM16 8– ...
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... Misaligned destination address Exceptions: I Instruction Type Register index of operand Register index of operand rB Instruction Fields: IMM16 = 16-bit signed immediate value Nios II Processor Reference Handbook branch if greater than or equal unsigned IMM16 Chapter 8: Instruction Set Reference Instruction Set Reference 0x2e December 2010 Altera Corporation 0 ...