IPR-NIOS Altera, IPR-NIOS Datasheet - Page 133
IPR-NIOS
Manufacturer Part Number
IPR-NIOS
Description
IP NIOS II MEGACORE RENEW
Manufacturer
Altera
Type
MegaCorer
Datasheet
1.IP-NIOS.pdf
(294 pages)
Specifications of IPR-NIOS
License
Renewal License
Lead Free Status / RoHS Status
Not applicable / Not applicable
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NII51015-10.1.0
Introduction
Table 5–1. Nios II Processor Cores (Part 1 of 3)
Nios II Processor Reference Handbook
December 2010
December 2010
NII51015-10.1.0
Objective
Performance
Area
Pipeline
f
DMIPS/MHz
Max. DMIPS
Max. f
Feature
This document describes all of the Nios
at the time of publishing. This document describes only implementation-specific
features of each processor core. All cores support the Nios II instruction set
architecture.
For more information regarding the Nios II instruction set architecture, refer to the
Instruction Set Reference
For common core information and details on a specific core, refer to the appropriate
section:
■
■
■
■
Table 5–1
table is designed to help system designers choose the core that best suits their target
application.
MAX
“Device Family Support” on page 5–3
“Nios II/f Core” on page 5–4
“Nios II/s Core” on page 5–14
“Nios II/e Core” on page 5–20
(2)
(1)
(2)
compares the objectives and features of each Nios II processor core. The
Minimal core size
0.15
31
200 MHz
< 700 LEs;
< 350 ALMs
1 stage
chapter of the Nios II Processor Reference Handbook.
5. Nios II Core Implementation Details
Nios II/e
®
Small core size
0.74
127
165 MHz
< 1400 LEs;
< 700 ALMs
5 stages
II processor core implementations available
Nios II/s
Core
6 stages
Fast execution speed
1.16
218
185 MHz
With MMU:
With MPU:
Without MMU or MPU:
< 1800 LEs;
< 900 ALMs
< 3000 LEs;
< 1500 ALMs
< 2400 LEs;
< 1200 ALMs
Nios II/f
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