IPTR-DSPBUILDER Altera, IPTR-DSPBUILDER Datasheet

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... DSP Builder Handbook Volume 2: DSP Builder Standard 101 Innovation Drive San Jose, CA 95134 www.altera.com HB_DSPB_STD-1.0 Blockset Document Version: 1.0 Document Date: June 2010 ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

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... Add the DSP Builder Design to the Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–21 Chapter 3. Design Rules and Procedures DSP Builder Naming Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1 Using a MATLAB Variable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Fixed-Point Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 Binary Point Location in Signed Binary Fractional Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–3 © June 2010 Altera Corporation DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary Contents ...

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... Parameterizing the FIR Compiler Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Generating the FIR Compiler Function Variation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Adding Stimulus and Scope Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–5 Simulating the Design in Simulink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–8 Compiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–9 Performing RTL Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–10 DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary © June 2010 Altera Corporation ...

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... Testing the DSP Builder Block from Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–15 Avalon-MM FIFO Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16 Opening the Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–16 Compiling the Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–17 Instantiating the Design in SOPC Builder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7–18 © June 2010 Altera Corporation DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary v ...

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... Exporting HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–2 Using Exported HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 Migration of DSP Builder (Standard Blockset) Files to a New Location . . . . . . . . . . . . . . . . . . . . . . . . . 12–4 Integration of Multiple Models in a Top-Level Quartus II Project . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–5 Design Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12–6 DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary © June 2010 Altera Corporation ...

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... Check the Software Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 DSP Development Board Troubleshooting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 SignalTap II Analysis Appears to Hang . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 Error if Output Block Connected to an Altera Synthesis Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–5 Warning if Input/Output Blocks Conflict with clock or aclr Ports . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 Wiring the Asynchronous Clear Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 Error Issues when a Design Includes Pre-v7.1 Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–6 Creating an Input Terminator for Debugging a Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13– ...

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... LFSR Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–14 Logical Bit Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–16 Logical Bus Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–17 Logical Reduce Operator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–19 Multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20 Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–22 Single Pulse . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–23 Chapter 5. Interfaces Library Avalon-MM Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3 DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary © June 2010 Altera Corporation ...

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... Dual-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–7 FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–10 LUT (Look-Up Table 9–11 Memory Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–13 Parallel To Serial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–14 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–16 Serial To Parallel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–18 Shift Taps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–20 Single-Port RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9–21 © June 2010 Altera Corporation DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary ix ...

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... Imaging Edge Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–8 Quartus II Assignment Setting Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–8 SignalTap II Filtering Lab . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–8 SignalTap II Filtering Lab with DAC to ADC Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9 Cyclone II DE2 Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9 Cyclone II EP2C35 DSP Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13–9 DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary © June 2010 Altera Corporation ...

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... IO & Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–3 Rate Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–4 Simulation Blocks Library . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–4 State Machine Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–4 Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–4 Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14–5 Additional Information How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info–1 © June 2010 Altera Corporation DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary xi ...

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... DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary © June 2010 Altera Corporation ...

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... The following table shows the revision dates for the sections in this volume. Section DSP Builder Standard Blockset User Guide DSP Builder Standard Blockset Libraries © June 2010 Altera Corporation Preliminary Section Revision Dates Version Date 1.0 June 2010 HB_DSPA_STD_UG-1.0 1.0 June 2010 HB_DSPA_STD_LIB-1 ...

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... DSP Builder Handbook Volume 2: DSP Builder Standard Blockset Preliminary Section Revision Dates © June 2010 Altera Corporation ...

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... Section I. DSP Builder Standard Blockset User Guide 101 Innovation Drive San Jose, CA 95134 www.altera.com HB_DSPA_STD_UG-1.0 Document Version: 1.0 Document Date: June 2010 ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

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... Revision History The following table shows the revision history for this section. Date Version June 2010 1.0 First published. © June 2010 Altera Corporation About This Section Changes Made DSP Builder Standard Blockset User Guide Preliminary ...

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... DSP Builder Standard Blockset User Guide Preliminary About This Section Revision History © June 2010 Altera Corporation ...

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... Release Information Table 1–1 provides information about this release of DSP Builder. Table 1–1. DSP Builder Release Information Version Release Date Ordering Code Device Family Support DSP Builder supports the following Altera ■ Arria™ GX ■ Arria II GX ® ■ Cyclone Cyclone II ■ ...

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... Enables rapid prototyping using Altera DSP development boards. ■ Supports the SignalTap probes signals from the Altera device on the DSP board and imports the data into the MATLAB workspace to ease visual analysis. Allows HDL import of VHDL or Verilog HDL design entities and HDL defined in ■ ...

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... DSP design in an algorithm-friendly development environment. You can combine existing MATLAB functions and Simulink blocks with Altera DSP Builder blocks and Altera intellectual property (IP) MegaCore functions to link system-level design and implementation with DSP algorithm development. In this way, DSP Builder allows system, algorithm, and hardware designers to share a common development platform ...

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... DSP Builder Standard Blockset User Guide Preliminary Chapter 1: About DSP Builder General Description © June 2010 Altera Corporation ...

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... Quartus II project, you can use the quartus_map command in the Quartus II software to run a simulation netlist flow that generates files for Verilog HDL simulation. f For information about this flow, refer to the Quartus II help. © June 2010 Altera Corporation 2. Getting Started DSP Builder Standard Blockset User Guide Preliminary ...

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... If no base clock exists in your design, DSP Builder creates a default clock with a 20ns real-world period and a Simulink sample time of 1. You can derive additional clocks from the base clock by adding Clock_Derived blocks. DSP Builder Standard Blockset User Guide Preliminary Chapter 2: Getting Started Design Flow © June 2010 Altera Corporation ...

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... MATLAB and Simulink environment. You can synthesize and simulate the output files in other software tools without the Tcl scripts. In addition, the Testbench block generates a testbench and supporting files for VHDL simulation. © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 2–3 ...

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... Click the MATLAB Start button. Point to Simulink and click Library Browser. DSP Builder Standard Blockset User Guide “Design Flows for Synthesis, Compilation and Simulation” on section in volume 2 of the DSP Builder Handbook. Preliminary Chapter 2: Getting Started Creating the Amplitude Modulation Model DSP ® © June 2010 Altera Corporation ...

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... Table 2–1. Parameters for the Sine Wave Block Parameter Sine type Time Amplitude Bias Samples per period Number of offset examples Sample time Interpret vector parameters a 1-D © June 2010 Altera Corporation (Figure 2–3). (Table Value Sample based simulation time 2^15– ...

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... Add the SinIn Block To add the SinIn block, follow these steps the Simulink Library Browser, expand the Altera DSP Builder Blockset folder to display the DSP Builder libraries Figure 2–4. Altera DSP Builder Folder in the Simulink Library Browser 2. Select the IO & Bus library. ...

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... Add the Delay Block To add the Delay block, follow these steps: 1. Select the Storage library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. 2. Drag and drop the Delay block into your model and position it to the right of the SinIn block ...

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... Add the SinDelay and SinIn2 Blocks To add the SinDelay and SinIn2 blocks, follow these steps: 1. Select the IO & Bus library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. 2. Drag and drop two Output blocks into your model, positioning them to the right of the Delay block ...

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... Draw a connection line from the top left of the Mux block to the line between the SinIn2 block. 8. Draw a connection line from the SinIn2 block to the line between the SinIn and Delay blocks. Add the Random Bitstream Block To add the Random Bitstream block, follow these steps: © June 2010 Altera Corporation Value Signed Integer 16 Inferred 4 ...

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... Rename the Random Noise block Random Bitstream. Add the Noise Block To add the Noise block, follow these steps: 1. Select the IO & Bus library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. 2. Drag and drop an Input block into your model, positioning it to the right of the Random Bitstream block ...

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... The Bus Builder block converts a bit to a signed bus. To add the Bus Builder block, follow these steps: 1. Select the IO & Bus library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. 2. Drag and drop a Bus Builder block into your model, positioning it to the right of the Noise block ...

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... Add the StreamMod and StreamBit Blocks To add the StreamMod and StreamBit blocks, follow these steps: 1. Select the IO & Bus library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. 2. Drag and drop two Output blocks into your model, positioning them to the right of the Product block ...

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... Double-click the Scope block and click the Parameters ‘Scope’ parameters dialog box. 4. Set the Scope parameters Table 2–13. Parameters for the Scope Block Parameter Number of axes Time range Tick labels Sampling © June 2010 Altera Corporation (Table 2–12). Value Single Bit Inferred (Table 2–13). Value ...

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... Figure 2–7. Amplitude Modulation Design Example Add a Clock Block To add a Clock block, follow these steps: 1. Select the AltLab library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. 2. Drag and drop a Clock block into your model. 3. Double-click on the Clock block to display the Block Parameters dialog box. ...

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... Start time Stop time Type Solver f For detailed information about solver options, refer to the description of the Solver Pane in the Simulink Help. Figure 2–8. Configuration Parameters 3. Click OK. © June 2010 Altera Corporation (Table 2–15). Value 0.0 4e–6 Fixed-step discrete (no continuous states) Preliminary 2– ...

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... To create and compile a Quartus II project for your DSP Builder design, and to program your design onto an Altera FPGA, add a Signal Compiler block by following these steps: 1. Select the AltLab library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. 2. Drag and drop a Signal Compiler block into your model. ...

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... Performing RTL Simulation To perform RTL simulation with the ModelSim software, add a TestBench block, by following these steps: 1. Select the AltLab library from the Altera DSP Builder BlockSet folder in the Simulink Library Browser. 2. Drag and drop a TestBench block into your model. 3. Double-click on the new TestBench block. ...

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... Figure 2–11. Testbench Generator Dialog Box 4. Ensure that Enable Test Bench generation is on. DSP Builder Standard Blockset User Guide Preliminary Chapter 2: Getting Started Performing RTL Simulation © June 2010 Altera Corporation ...

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... Change the format of the sinin, sindelay and streammod signals to analog ModelSim 6.4a, you can right-click to display the popup menu, point to Format and click on Analog (Automatic). The user interface commands may be different in other versions of ModelSim. © June 2010 Altera Corporation (Figure 2–12). DSP Builder Standard Blockset User Guide Preliminary ...

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... Click New Project Wizard on the File menu in the Quartus II software and specify the working directory for your project. For example, D:\MyQuartusProject. DSP Builder Standard Blockset User Guide (“Compiling the Design” on page Preliminary Chapter 2: Getting Started Adding the Design to a Quartus II Project (Figure 2–13). 2–16). © June 2010 Altera Corporation ...

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... Compile the Quartus II design by clicking Start Compilation on the Processing menu. 1 You can copy the component declaration from the example file for your own code. © June 2010 Altera Corporation “Compiling the Design” on page DSP Builder Standard Blockset User Guide Preliminary 2–21 ...

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... DSP Builder Standard Blockset User Guide Adding the Design to a Quartus II Project Preliminary Chapter 2: Getting Started © June 2010 Altera Corporation ...

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... VHDL entity. Avoid using VHDL keywords for DSP Builder port names. ■ ■ Do not use illegal characters. VHDL identifier names can contain only and underscore (_) characters. © June 2010 Altera Corporation 3. Design Rules and Procedures DSP Builder Standard Blockset User Guide Preliminary ...

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... A Simulink SBF signal A[L].[R] maps in VHDL to STD_LOGIC_VECTOR({ DOWNTO 0) A Simulink signed binary signal A[L] maps to STD_LOGIC_VECTOR({ DOWNTO 0) A Simulink unsigned binary signal A[L] maps to STD_LOGIC_VECTOR({ DOWNTO 0) Preliminary Chapter 3: Design Rules and Procedures Using a MATLAB Variable DSP Builder Simulink-to-HDL Translation (1), (2) © June 2010 Altera Corporation ...

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... DSP Builder represents the fixed-point signals in the following signed binary fractional (SBF) format: [number of bits].[]—represents the number of bits to the left of the binary point ■ including the sign bit. © June 2010 Altera Corporation Notation A Simulink single bit integer signal maps to STD_LOGIC Preliminary 3– ...

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... Delay block. Data Width Propagation You can specify the bit width of many Altera blocks in the Simulink design. However, you do not need to specify the bit width for all blocks. If you do not specify explicitly the bit width, DSP Builder assigns a bit width during the Simulink-to-VHDL conversion by propagating the bit width from the source of a datapath to its destination ...

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... Input block, which is an 8-bit input bus. This bus feeds the register U0, which feeds U1, which feeds U2. DSP Builder propagates the 8-bit bus in this register chain where each register is eight bits wide © June 2010 Altera Corporation (Figure 3–4). DSP Builder Standard Blockset User Guide Preliminary 3– ...

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... The output bit width of the parallel adder is 18 bits, which covers the full resolution. DSP Builder Standard Blockset User Guide Chapter 3: Design Rules and Procedures 2  yout k    c i   – Preliminary Bit Width Design Rule © June 2010 Altera Corporation ...

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... You can also achieve bus conversion by inserting an AltBus, Round, or Saturate block. The RTL view illustrates the effect of this truncation. The parallel adder required has a smaller bit width and the synthesis tool reduces the size of the multiplier to have a 9-bit output © June 2010 Altera Corporation (Figure 3–7). Preliminary 3–7 ...

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... DSP Builder blocks use a sampling frequency of 1. You can use the Clock block to change the Simulink sample period and the hardware clock period. DSP Builder Standard Blockset User Guide Chapter 3: Design Rules and Procedures “Fixed-Point Notation” on page Preliminary Frequency Design Rules 3–2. © June 2010 Altera Corporation ...

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... Dual-Clock FIFO block where the sampling period of the read input port is expected to be different than the sampling period of the write input port. © June 2010 Altera Corporation for more information. illustrates an incorrect use of the DSP Builder Logical Bit Preliminary 3– ...

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... DSP Builder Standard Blockset User Guide (Figure shows a stable hardware implementation. Preliminary Chapter 3: Design Rules and Procedures Frequency Design Rules 3–9). © June 2010 Altera Corporation ...

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... DSP Builder blocks fall into the following clocking categories: Combinational blocks—the output always changes at the same sample time slot as ■ the input. Registered blocks—the output changes after a variable number of sample time ■ slots. © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 3–11 ...

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... For feedback circuitry (the output of a block fed back into the input of a block), a registered block must be in the feedback loop. Otherwise, DSP Builder creates an unresolved combinational loop DSP Builder Standard Blockset User Guide Chapter 3: Design Rules and Procedures (Figure 3–13). Preliminary Frequency Design Rules © June 2010 Altera Corporation ...

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... The Delay block is enabled on the 2nd phase out of 4 and only the 2nd data out of 4 (sampled at the rate 1) passes through. The data on phases 1, 3, and 4 does not pass through the Delay block. © June 2010 Altera Corporation shows some examples of typical clock phase selections. Description Preliminary 3– ...

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... For information about the built-in PLLs, refer to the device handbook for the device family you are targeting. Figure 3–15 shows an example of multiple-clock domain support using the PLL block. Figure 3–15. MultipleClockDelay.mdl DSP Builder Standard Blockset User Guide Chapter 3: Design Rules and Procedures Preliminary Frequency Design Rules © June 2010 Altera Corporation ...

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... Add the DSP Builder .mdl file to the Quartus II project as a source file. ■ Create a top-level design that instantiates your ALTPLL variation and your DSP Builder design. © June 2010 Altera Corporation Figure 3–15) operates on output clock PLL_clk0 and datapath 3–15) operates on output clock PLL_clk1. Specify these clocks by Preliminary 3– ...

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... DSP Builder Standard Blockset User Guide Chapter 3: Design Rules and Procedures Timing Semantics Between Simulink and HDL Simulation (Figure 3–17 on page Preliminary 3–18). © June 2010 Altera Corporation ...

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... A Global Reset block (SCLR), which corresponds to this hardware signal is in the Altera DSP Builder Blockset IO & Bus library. The global reset signal is reset before meaningful simulation. When converting from the Simulink domain to the hardware domain, the reset period is before the Simulink simulation begins ...

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... In general, DSP Builder is not cycle-accurate when crossing clock domains. Figure 3–18. Multiple-Clock Timing Relationships DSP Builder Standard Blockset User Guide Chapter 3: Design Rules and Procedures Timing Semantics Between Simulink and HDL Simulation Preliminary Figure 3–18 shows © June 2010 Altera Corporation ...

Page 63

... Typically, you connect these blocks to the Simulink simulation blocks for your testbench. An Output block should not connect to another Altera block. If you connect more Altera blocks (that map to HDL), empty ports are created and the HDL does not compile for synthesis. ...

Page 64

... For information about naming the Subsystem block instances, refer to Naming Conventions” on page DSP Builder Standard Blockset User Guide Figure 3–19 illustrates a hierarchy for a design fir3tap.mdl, which 3–1. Preliminary Chapter 3: Design Rules and Procedures Hierarchical Design “DSP Builder © June 2010 Altera Corporation ...

Page 65

... Figure 3–20. Goto & From Block Example Use the Goto blocks ([ReadAddr], [WriteAddr], and [WriteEna] with the From blocks ([ReadAddr], [WriteAddr], and [WriteEna], which connect to the dual-port RAM blocks. © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 3–21 ...

Page 66

... DSP Builder Standard Blockset User Guide “Subsystem Builder Design Example” “HDL Import Design Example” in Chapter (Figure 3–21 on page 3–23). Preliminary Chapter 3: Design Rules and Procedures Create Black Box and HDL Import in Chapter 8. in Chapter 8. 2. © June 2010 Altera Corporation ...

Page 67

... Signal Compiler. The Tcl file can include any number of Quartus II assignments with the syntax: set_global_assignment -name <assignment> <value> f For detailed information about Quartus II assignments, refer to the File Reference © June 2010 Altera Corporation Manual. Manual. Preliminary 3–23 Quartus II Settings ...

Page 68

... The HDL Import blocks in your design may need updating if you upgrade from a previous software version or move a design to a different workstation. DSP Builder Standard Blockset User Guide 3–2. (Figure 3–22). The selected mode shows on the Display Pipeline Preliminary Chapter 3: Design Rules and Procedures Displaying Port Data Types © June 2010 Altera Corporation ...

Page 69

... To analyze the hardware resources required for your design with a Resource Usage block, follow these steps: 1. Select the AltLab library from the Altera DSP Builder BlockSet folder in the Simulink Library Browser. 2. Drag and drop a Resource Usage block into your model and double-click on the block to open the Resource Usage dialog box ...

Page 70

... For a more complex example, the entire critical path through your design may highlight. DSP Builder Standard Blockset User Guide Figure 3–24 shows the hardware resources that the Product block Preliminary Chapter 3: Design Rules and Procedures Analyzing the Hardware Resource Usage © June 2010 Altera Corporation ...

Page 71

... Using the Quartus II Assignment Editor and Node Finder tools, you can identify the names of the registers and make the assignments to them. For example, if your model is my_model, the names may be: my_model_GN:auto_inst|alt_dspbuilder_delay_GNLVAGVO3B:Delay|alt_dsp builder_SDelay:Delay1i|DelayLine my_model_GN:auto_inst|alt_dspbuilder_delay_GNLVAGVO3B:Delay1|alt_ds pbuilder_SDelay:Delay1i|DelayLine © June 2010 Altera Corporation to prevent them from merging. Preliminary 3–27 DSP Builder Standard Blockset User Guide ...

Page 72

... This type of assignment can be useful for a complicated block that contains many registers when you want the assignment to apply to all of the registers. DSP Builder Standard Blockset User Guide Chapter 3: Design Rules and Procedures Making Quartus II Assignments to Block Entity Names Preliminary © June 2010 Altera Corporation ...

Page 73

... MegaCore library. Running this command, creates a MegaCore Functions subfolder below the Altera DSP Builder Blockset in the Simulink Library Browser. In this folder, there is a blue block with a version name for each of the installed MegaCore functions. © ...

Page 74

... The correct version number still shows on the body of the block. Altera recommends that you rename all blocks representing MegaCore functions with a name describing their use in your design. Using unique block names ensures that all the generated entities for the same MegaCore function in a hierarchical design also have unique names ...

Page 75

... Connecting the MegaCore Function Variation Block to the Design The Simulink block now has the required input and output ports as parameterized in IP Toolbench or the MegaWizard interface. You can connect these ports to other Altera DSP Builder blocks in your Simulink design. Simulating the MegaCore Function Variation in the Model You can simulate the Simulink block representing the MegaCore function variation like any other block from the Simulink Library Browser ...

Page 76

... On the View menu In your Simulink model window, click Library Browser. The Simulink Library Browser displays. 2. Select the MegaCore Functions library from the Altera DSP Builder Blockset folder in the Simulink Library Browser Figure 4–1. MegaCore Functions Library 3. Drag and drop a blue versioned fir_compiler_v9.0 block into your model (Figure 4– ...

Page 77

... Figure 4–3. FIR Compiler Block in Simulink Model After Generation Adding Stimulus and Scope Blocks To create a sample design to test the low-pass filter by feeding the filter two sine waves (Figure 4–4 on page © June 2010 Altera Corporation “DSP Builder Naming Conventions” on page FIR Compiler User Guide. (Figure 4– ...

Page 78

... Connect the outputs from the Sine Wave and Sine Wave1 blocks to an Add block (from the Simulink Math Operations library). 5. Add an Input block (from the IO & Bus library in the Altera DSP Builder Blockset) and connect it between the Add block and the ast_sink_data pin on the my_fir_compiler block ...

Page 79

... Rounding Mode Saturation Mode Specify Clock 10. Repeat Step 11. Add a Single Pulse block (from the Gate & Control library in the Altera DSP Builder Blockset) and connect it to the reset_n pin on the my_fir_compiler block. 12. Use the Block Parameters dialog box to set the parameters Table 4– ...

Page 80

... Figure 4–5. Configuration Parameters: mc_example/Configuration Dialog Box 2. Select the Solver page and set the parameters DSP Builder Standard Blockset User Guide Chapter 4: Using MegaCore Functions MegaCore Function Design Example (Figure 4–5 on page (Table 4–6). Preliminary 4–8). © June 2010 Altera Corporation ...

Page 81

... To create and compile a Quartus II project for your DSP Builder design, and to program your design onto an Altera FPGA, add a Signal Compiler block. Follow these steps: 1. Select the AltLab library from the Altera DSP Builder Blockset folder in the Simulink Library Browser. 2. Drag and drop a Signal Compiler block into your model. ...

Page 82

... Performing RTL Simulation To perform RTL simulation with the ModelSim software, add a TestBench block. Follow these steps: 1. Select the AltLab library from the Altera DSP Builder BlockSet folder in the Simulink Library Browser. 2. Drag and drop a TestBench block into your model. 3. Double-click on the new TestBench block. The TestBench Generator dialog box ...

Page 83

... Chapter 4: Using MegaCore Functions MegaCore Function Design Example Figure 4–8. TestBench Generator Dialog Box 4. Ensure that Enable Test Bench generation is on. 5. Click the Advanced Tab © June 2010 Altera Corporation (Figure 4–9). DSP Builder Standard Blockset User Guide Preliminary 4–11 ...

Page 84

... Wave Properties dialog box to change the format to Analog with height 75 and scale 0.001. DSP Builder Standard Blockset User Guide 10 for the output signal in the ModelSim Wave window and use the Preliminary Chapter 4: Using MegaCore Functions MegaCore Function Design Example © June 2010 Altera Corporation ...

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... DSP Builder stores the files that support the configuration and simulation of a MegaCore function variation in a subdirectory of the directory containing your Simulink MDL file DSPBuilder_<design name>_import. When copying a design from one location to another, make sure that you also copy this subdirectory. © June 2010 Altera Corporation 4–10). Preliminary 4–13 ...

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... Most of the MegaCore functions available in DSP Builder use the IP Toolbench interface. DSP Builder Standard Blockset User Guide Figure 4–11, DSP Builder cannot tie the reset to a constant because the Preliminary Chapter 4: Using MegaCore Functions MegaCore Functions Design Issues © June 2010 Altera Corporation ...

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... If you change the device family in Signal Compiler, you must check that any IP Toolbench MegaCore functions have the correct device family set to ensure that the simulation models and generated hardware are consistent. © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary ...

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... DSP Builder Standard Blockset User Guide Chapter 4: Using MegaCore Functions MegaCore Functions Design Issues Preliminary © June 2010 Altera Corporation ...

Page 89

... HIL block, and discusses the optional burst and frame data transfer modes. HIL Design Flow The HIL block in AltLab library of the Altera DSP Builder Blockset enables the HIL functionality. It represents the functions implemented on your FPGA, and works smoothly with the normal DSP Builder/Simulink work flow. ...

Page 90

... A JTAG download cable (for example, a ByteBlasterMV™, ByteBlaster™ II, ■ ByteBlaster, MasterBlaster™, or USB-Blaster™ cable). A maximum of one HIL block for each JTAG download cable. ■ DSP Builder Standard Blockset User Guide Preliminary Chapter 5: Using HIL HIL Requirements © June 2010 Altera Corporation ...

Page 91

... Frequency sweep This section shows the frequency sweep design. 1 This tutorial uses the Stratix II hardware device on an Altera Stratix II EP2S60 DSP Development Board. However, you can also use any other supported device and development board. To create a frequency sweep design, follow these steps: 1. Run MATLAB, and open the model FreqSweep.mdl in the < ...

Page 92

... Open the model FreqSweep_HIL.mdl from the FreqSweep directory (step 1). Figure 5–4 Figure 5–4. Frequency Sweep Design Model Using the HIL Block DSP Builder Standard Blockset User Guide shows this model, with the HIL block in place. Preliminary Chapter 5: Using HIL HIL Design Example © June 2010 Altera Corporation ...

Page 93

... Click Scan Jtag to find available cables and hardware devices in the chain. 15. Select the JTAG download cable that references the required FPGA device and click Configure FPGA to program the FPGA on the board. 16. Click Close. © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 5–5 ...

Page 94

... Low SLD overhead. A latency is introduced on the output signals of ■ the HIL block making feedback loop difficult Fast HIL results. ■ outside the FPGA device. Frame mode possible. ■ Preliminary Chapter 5: Using HIL Burst and Frame Modes Disadvantages © June 2010 Altera Corporation ...

Page 95

... HIL as 0x800000 byte in size. When the data record size (max of total input bits and output bits × burst length × 2 (for both input and output) exceeds this number, DSP Builder resets the burst length to 1. © June 2010 Altera Corporation 5–6). Figure 5–8 Preliminary 5– ...

Page 96

... Stratix II target device family, with a transform length of 64 points, data precision of 16 bits, and twiddle precision of 16 bits. DSP Builder Standard Blockset User Guide 5–7). Frame mode builds on the burst functionality Preliminary Chapter 5: Using HIL Burst and Frame Modes © June 2010 Altera Corporation ...

Page 97

... Refer to the FFT MegaCore Function User Guide input and output port signal timing. © June 2010 Altera Corporation shows the FFT design with a HIL block (and the parameters 5–7). for additional information about the DSP Builder Standard Blockset User Guide Preliminary 5– ...

Page 98

... Scan JTAG Fails to Find Correct Cable or Device This issue occurs if you connect the target DSP development board switch it on after you open the HIL dialog box. DSP Builder Standard Blockset User Guide Preliminary Chapter 5: Using HIL Troubleshooting HIL Designs © June 2010 Altera Corporation ...

Page 99

... LED on the DSP development board. The SignalTap II logic analyzer captures the signal activity at the output of the two AND gates and the incrementer of the design loads into the Altera device on the development board. The logic analyzer retrieves the values and displays them in the MATLAB work space ...

Page 100

... The SignalTap II logic analyzer triggers when it detects the trigger pattern on the input signals. SignalTap II Example Designs Altera provides several example designs DSP Builder Standard Blockset User Guide Chapter 6: Performing SignalTap II Logic Analysis section in volume 2 of the DSP Builder Handbook. (Figure 6–1). Preliminary SignalTap II Example Designs DSP © June 2010 Altera Corporation ...

Page 101

... Adding the Configuration and Connector Blocks You must add the board configuration block and connector blocks for the board that you want to use. This tutorial uses the Cyclone II EP2C35 development board. © June 2010 Altera Corporation “Turning On the SignalTap II Option in Signal Compiler” on page Preliminary 6– ...

Page 102

... Select the Boards library from the Altera DSP Builder Blockset folder in the Simulink library browser. 2. Open the CycloneIIEP2C35 folder. Drag and drop the Cyclone II EP2C35 DSP Development Board configuration block into your model. 3. Drag and drop the SW2 and SW3 blocks close to the AND_Gate2 block in your model ...

Page 103

... AND_Gate1 block and the OR_Gate block (Figure 6–4 you position the block with this method, the Simulink software inserts the block and joins connection lines on both sides. © June 2010 Altera Corporation Value Time based Use Simulation time 1 2 ...

Page 104

... Verify that the Enable SignalTap II option is on. When this option is on, Signal Compiler inserts an instance of the SignalTap II logic analyzer into your design. DSP Builder Standard Blockset User Guide Chapter 6: Performing SignalTap II Logic Analysis Preliminary SignalTap II Example Designs © June 2010 Altera Corporation ...

Page 105

... To perform analysis, follow these steps: 1. Click Scan Jtag in the SignalTap II Logic Analyzer dialog box and select the appropriate download cable and device. 2. Click Acquire. © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 6–7 ...

Page 106

... MATLAB plot for the SignalTap II node firstandout. shows the MATLAB plot for the SignalTap II node secondandout. shows the MATLAB plot for the SignalTap II node cntout. Preliminary Chapter 6: Performing SignalTap II Logic Analysis SignalTap II Example Designs © June 2010 Altera Corporation ...

Page 107

... For more information about the SignalTap II Logic Analyzer block, refer to the SignalTap II Logic Analyzer block description in the AltLab Library chapter in the DSP Builder Standard Blockset Libraries Handbook. © June 2010 Altera Corporation section in volume 2 of the DSP Builder DSP Builder Standard Blockset User Guide Preliminary ...

Page 108

... DSP Builder Standard Blockset User Guide Chapter 6: Performing SignalTap II Logic Analysis Preliminary SignalTap II Example Designs © June 2010 Altera Corporation ...

Page 109

... For more information about SOPC Builder, refer to the SOPC Builder; for more information about the Avalon-MM Interface, refer to the Avalon Interface © June 2010 Altera Corporation 7. Using the Interfaces Library provide peripheral designers with a basis for Specifications. Preliminary Quartus II Handbook Volume 4: ...

Page 110

... For more information about these signals, refer to the Libraries section in volume 2 of the DSP Builder Handbook. DSP Builder Standard Blockset User Guide Chapter 7: Using the Interfaces Library DSP Builder Standard Blockset Preliminary Avalon-MM Interface Blocks © June 2010 Altera Corporation ...

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... Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Figure 7–1 shows a block that describes an Avalon-MM slave interface where all the Avalon-MM signals are enabled. Figure 7–1. Avalon-MM Slave Block Signals © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 7–3 ...

Page 112

... Avalon-MM signals are enabled. DSP Builder Standard Blockset User Guide Figure 7–1 shows between the ports. DSP Builder Standard Blockset shows a block that describes an Avalon-MM master interface Preliminary Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks © June 2010 Altera Corporation ...

Page 113

... Data, Valid, and Ready. To provide a high level view, DSP Builder provides you with configurable Avalon-MM Write FIFO and Avalon-MM Read FIFO blocks for you to map Avalon-MM interface signals to this protocol. © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary ...

Page 114

... You can use this design as a template to design new functionality (for example, when you use an Avalon-MM address input to split incoming streams). DSP Builder Standard Blockset User Guide Chapter 7: Using the Interfaces Library Preliminary Avalon-MM Interface Blocks © June 2010 Altera Corporation ...

Page 115

... You can open the hierarchy below the Avalon-MM Read FIFO block by right-clicking on the block and choosing Look Under Mask from the pop-up menu. Figure 7–5 shows the internal content of an Avalon-MM Read FIFO. © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 7–7 ...

Page 116

... To complete the design example, follow these steps: 1. Click Open on the File menu in the MATLAB software. 2. Browse to the <DSP Builder install path>\DesignExamples\Tutorials\ SOPCBuilder\SOPCBlock directory. DSP Builder Standard Blockset User Guide Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example Preliminary © June 2010 Altera Corporation ...

Page 117

... Rename the file by clicking Save As on the File menu. Create a new folder MySystem and save your new MDL file as topavalon.mdl in this folder. 5. Open the Simulink Library Browser. Expand the Altera DSP Builder Blockset and select Avalon Memory-Mapped in the Interfaces library. 6. Drag and drop an Avalon-MM Slave block into the top left of your model. ...

Page 118

... For more information, refer to the Boards Library chapter in the the DSP Builder Handbook. DSP Builder Standard Blockset User Guide Avalon-MM Interface Blocks Design Example (Figure 7–7). DSP Builder Standard Blockset Libraries Preliminary Chapter 7: Using the Interfaces Library section in volume 2 of © June 2010 Altera Corporation ...

Page 119

... Click Compare against HDL. This process generates HDL, runs Simulink and ModelSim, and then compares the simulation results. Progress messages issue in the dialog box and completes with a message “Exact Match”. © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 7–11 ...

Page 120

... Create New System dialog box: a. Specify SOPC as the system name. b. Select VHDL for the target HDL. c. Click OK. DSP Builder Standard Blockset User Guide ® II software. Preliminary Chapter 7: Using the Interfaces Library Avalon-MM Interface Blocks Design Example © June 2010 Altera Corporation ...

Page 121

... Finish to accept the default settings. i. Expand DSPBuilder Systems and double-click the topavalon_interface module to include it in your Nios II system Figure 7–9. Including Your DSP Builder Design Module in SOPC Builder © June 2010 Altera Corporation (Figure 7–9). DSP Builder Standard Blockset User Guide Preliminary 7– ...

Page 122

... Close the Quartus II Programmer window. DSP Builder Standard Blockset User Guide Avalon-MM Interface Blocks Design Example (Table 7–1) (depending on which development Direction Location Input PIN_AM17 Input PIN_AG19 Input PIN_N2 Input PIN_A14 Preliminary Chapter 7: Using the Interfaces Library © June 2010 Altera Corporation ...

Page 123

... Avalon-MM Interface Blocks Design Example Testing the DSP Builder Block from Software Altera provides a C program that loads a set of four coefficient into the filter, reads them back, and then repeats the process. To use this program, follow these steps the Nios II menu in SOPC Builder, click Nios II IDE. ...

Page 124

... Select the sopc_edge_detector.mdl file and click Open. Figure 7–10 shows sopc_edge_detector.mdl. DSP Builder Standard Blockset User Guide AN 351: Simulating Nios II Embedded Processor ® II embedded processor in SOPC Builder. Design. Preliminary Chapter 7: Using the Interfaces Library Avalon-MM FIFO Design Example Designs. AN364: Edge © June 2010 Altera Corporation ...

Page 125

... Double-click the Signal Compiler block. 2. Select the family and device for the DSP Development board you are using. The design example is configured for a Stratix 1S25 board 3. Click Compile. © June 2010 Altera Corporation (“Avalon-MM Interface Blocks Design “Verifying the Design” on page 7–11). ...

Page 126

... Instantiating the Design in SOPC Builder To instantiate your design as a custom peripheral to the Nios II embedded processor in SOPC Builder, follow these steps: 1. Start the Quartus II software. DSP Builder Standard Blockset User Guide Chapter 7: Using the Interfaces Library Preliminary Avalon-MM FIFO Design Example © June 2010 Altera Corporation ...

Page 127

... You can now design the rest of your NIOS embedded processor with the standard SOPC Builder design flow. f For more detailed instructions, refer to page 7–12 in the © June 2010 Altera Corporation “Instantiating the Design in SOPC Builder” on “Avalon-MM Interface Blocks Design Preliminary 7–19 Example”. ...

Page 128

... DSP Builder Standard Blockset User Guide Chapter 7: Using the Interfaces Library Avalon Interface Specifications. You can combine define how to convey data between a source Figure 7–12 shows the interaction that occurs between Preliminary Avalon-ST Interface © June 2010 Altera Corporation ...

Page 129

... Figure 7–13. Packetized Data Transfer The Avalon Interface Specifications transfer of data associated with multiple channels. Altera recommends that you achieve this mechanism with packet based transfers where each packet has a deterministic format and each channel is allocated a specific field (time slot in a packet). ...

Page 130

... Specifications. For an example of a design that uses Avalon-ST interfaces and the Packet Format Converter blocks, refer to Wireless Systems. DSP Builder Standard Blockset User Guide Chapter 7: Using the Interfaces Library AN442: Tool Flow for Design of Digital IF for Preliminary Avalon-ST Interface Avalon Interface © June 2010 Altera Corporation ...

Page 131

... The following sections show an example of importing an existing VHDL design into the DSP Builder environment with the HDL Import block. © June 2010 Altera Corporation 8. Using Black Boxes for HDL Subsystems DSP Builder Standard Blockset Libraries section in volume 2 of the DSP Builder ...

Page 132

... It is missing the main filter function, which you can import as HDL. 3. Rename the file by clicking Save As on the File menu. Name your new MDL file MyFilter.mdl. 4. Open the Simulink Library Browser. Expand the Altera DSP Builder Blockset and select the AltLab library. 5. Drag and drop a HDL Import block into your model. ...

Page 133

... Turn on the option to Sort top-level ports by name. 11. Under Generate Simulink Model, click Compile to generate a Simulink simulation model for the imported HDL design. Figure 8–1. HDL Import Dialog Box © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 8–3 ...

Page 134

... Click the Zoom X-axis icon and drag the cursor to zoom in on the first 70 X-axis time units. Figure 8–3 on page 8–5 DSP Builder Standard Blockset User Guide Chapter 8: Using Black Boxes for HDL Subsystems (Figure shows the simulation results. Preliminary HDL Import Design Example 8–2). The code © June 2010 Altera Corporation ...

Page 135

... Figure 8–4. Simulink Simulation Results for the Chirp Stimulus The HDL import tutorial is complete. You can optionally compile your model for synthesis or perform RTL simulation on your design by following similar procedures to those described in the © June 2010 Altera Corporation shows the simulation results. “Getting Started”. ...

Page 136

... Open the Simulink Library Browser and expand the AltLab library under the Altera DSP Builder blockset. 4. Drag a Subsystem Builder block into your model. DSP Builder Standard Blockset User Guide Chapter 8: Using Black Boxes for HDL Subsystems Subsystem Builder Design Example DSP Builder Standard Blockset Libraries Preliminary © June 2010 Altera Corporation ...

Page 137

... This action builds the subsystem and adds the signals for the fir_vhdl subsystem to the symbol in your filter8tap.mdl model. The Subsystem Builder dialog box automatically closes. 7. Connect the ports Figure 8–6. filter8tap Design © June 2010 Altera Corporation (Figure (Figure 8–6). Preliminary 8– ...

Page 138

... Leave the S-function modules parameter with its default value. 5. Click the Edit button to view the code that describes the S-Function. DSP Builder Standard Blockset User Guide Chapter 8: Using Black Boxes for HDL Subsystems Subsystem Builder Design Example Preliminary © June 2010 Altera Corporation ...

Page 139

... SS_DOUBLE); ssSetNumContStates(S, 0); ssSetNumDiscStates(S, 1); ssSetNumSampleTimes(S, 1); ssSetNumRWork(S, 0); ssSetNumIWork(S, 0); ssSetNumDWork(S, DYNAMICALLY_SIZED); // reserve element in the ssSetNumModes(S, 0); © June 2010 Altera Corporation /* Number of expected parameters */ 0); 0, SS_DOUBLE); // pointers vector to store a C++ object DSP Builder Standard Blockset User Guide Preliminary 8–9 ...

Page 140

... S-function. Initialize the vectors of this S-function. Compute the signals that this block emits. Update the states of the block. Perform any actions required at termination of simulation. (Figure 8–8). Preliminary Subsystem Builder Design Example Description © June 2010 Altera Corporation ...

Page 141

... ModelSim when your design is run using the TestBench block. The Quartus II software executes any files ending with _add.tcl when it creates the project. ModelSim executes files ending with _add_msim.tcl when it compiles your design testbench. © June 2010 Altera Corporation shows the simulation results. Preliminary 8–11 ...

Page 142

... Simulate the Design in ModelSim To test the simulation model against the HDL in ModelSim, follow these steps the Simulink Library Browser, expand AltLab library under Altera DSP Builder Blockset. 2. Drag a TestBench block into your model. 3. Double-click on the TestBench block and click Compare against HDL. ...

Page 143

... A parameterizable custom library block is a Simulink subsystem in which DSP Builder primitives describe the block functionality. This design flow also supports parameterizable hierarchical subsystem structures. Altera provides an example of a custom library block, <DSP Builder install path>\ DesignExamples\Tutorials\BuildingCustomLibrary\top.mdl. Figure 9–1. top.mdl Example The RamBasedDelay block that top.mdl uses example of a custom parameterizable Simulink block ...

Page 144

... To add functionality to the DelayFIFO block, follow these steps: 1. Double-click on the DelayFIFO block to open the NewLib/DelayFIFO subsystem window. 2. Drag and drop a Shift Taps block from the Storage library in the Altera DSP Builder Blockset into your model window. Insert the Shift Taps block between the input and output blocks Figure 9– ...

Page 145

... Use the Mask Editor to create parameters for the DelayFIFO block by following these steps: 1. Right-click the DelayFIFO block in the NewLib model and click Mask Subsystem on the pop-up menu the Mask Editor dialog box set the parameters © June 2010 Altera Corporation (Table 9–2). Old Name InDin ...

Page 146

... Parameter Visible Opaque Fixed Autoscale port_label('input',1,'din'); port_label('input',2,'ena'); port_label('output',1,'dout'); fprintf('Delay %d',d) Delay d SubSystem AlteraBlockSet RAM-Based Delay Element Altera Corporation Preliminary Chapter 9: Using Custom Library Blocks Creating a Custom Library Block Value © June 2010 Altera Corporation ...

Page 147

... End of slblocks 3. Save the M-file with the file name slblocks.m in the same directory as NewLib.mdl. The next time that you display the Simulink library browser the custom library is available © June 2010 Altera Corporation (Figure 9–5). DSP Builder Standard Blockset User Guide Preliminary 9– ...

Page 148

... If you move or copy your design, synchronize your model containing these blocks by using the following command: alt_dspbuilder_refresh_user_library_blocks 1 This command calls automatically when you use either of the commands: alt_dspbuilder_refresh_hdlimport or alt_dspbuilder_refresh_megacore DSP Builder Standard Blockset User Guide Chapter 9: Using Custom Library Blocks Preliminary Synchronizing a Custom Library © June 2010 Altera Corporation ...

Page 149

... The file also contains a brief description of the component. Component Types There are three main types of component: single bit, fixed size bus, and selectable single bit. © June 2010 Altera Corporation 10. Adding a Board Library DSP Builder Standard Blockset Libraries DSP Builder Standard Blockset User Guide ...

Page 150

... The component has the following attributes: displayname= Specifies the name of the component, which the board ■ description file references. DSP Builder Standard Blockset User Guide Chapter 10: Adding a Board Library Preliminary Creating a New Board Description © June 2010 Altera Corporation ...

Page 151

... IO OUT" direction="Output" type="BIT[1,0]"> <documentation> Prototyping Area Pin Single Bit Output %pinlist% </documentation> <display width="90" height="26"> plot([ 19],[ 0]); fprintf('EVAL IO OUT \n%pinname% '); </display> </component> © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 10–3 ...

Page 152

... II XYZ Board</displayname> The following component subelements declare the components: ■ Single bit type examples: <component name="LED0" pin="Pin_E5"/> DSP Builder Standard Blockset User Guide Chapter 10: Adding a Board Library Preliminary Creating a New Board Description © June 2010 Altera Corporation ...

Page 153

... Input clock selection list --> <option name="ClockPinIn" label="Clock Pin In"> <pin location="Pin_N2"/> <pin location="Pin_N25"/> <pin location="Pin_AE14"/> <pin location="Pin_AF14"/> <pin location="None"/> © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 10–5 ...

Page 154

... Restart MATLAB without opening the Simulink library and run the following command in the MATLAB command window to create the new board library: alt_dspbuilder_createComponentLibrary DSP Builder Standard Blockset User Guide Chapter 10: Adding a Board Library Preliminary Building the Board Library © June 2010 Altera Corporation ...

Page 155

... When the address counter is equal to 0, the empty flag asserts ■ When the address counter is equal to 250, the full flag asserts. ■ © June 2010 Altera Corporation 11. Using the State Machine Library DSP Builder Standard Blockset User Guide Preliminary ...

Page 156

... DSP Builder Standard Blockset User Guide Chapter 11: Using the State Machine Library shows the default State Machine Table block. In this Preliminary Using the State Machine Table Block © June 2010 Altera Corporation ...

Page 157

... The current state and next state values must be state names defined in the States tab, which you can select from a list in the dialog box. © June 2010 Altera Corporation Condition (push=1)&(count_in!=250) (push=0)& ...

Page 158

... DSP Builder Standard Blockset User Guide shows the Conditional Statements tab, after defining the conditional Preliminary Chapter 11: Using the State Machine Library Using the State Machine Table Block © June 2010 Altera Corporation ...

Page 159

... Use the Move Up and Move Down buttons to change the order of the conditional statements Table 11–4. Idle State Condition Priority (Reordered) Current State idle idle idle idle © June 2010 Altera Corporation Description Negative 1 Brackets 1 Numeric equality 2 Not equal to 2 Greater than ...

Page 160

... Figure 11–5. fifo_controller Block After Closing the State Machine Table DSP Builder Standard Blockset User Guide Figure 11–4 shows the Design Rule Check tab after clicking shows the updated fifo_controller block. Preliminary Chapter 11: Using the State Machine Library Using the State Machine Table Block © June 2010 Altera Corporation ...

Page 161

... Figure 11–7. Quartus II State Machine Editor Window 3. On the Tools menu in the Quartus II State Machine Editor, point to State Machine Wizard and click Create a new state machine design. © June 2010 Altera Corporation Figure 11–6 shows the default State Machine Editor block. In this (Figure 11– ...

Page 162

... Preliminary Using the State Machine Editor Block 11–1). Condition © June 2010 Altera Corporation ...

Page 163

... June 2010 Altera Corporation shows the Transitions page after you define the states, inputs, and Preliminary 11–9 DSP Builder Standard Blockset User Guide ...

Page 164

... Chapter 11: Using the State Machine Library Using the State Machine Editor Block Output Value 1 empty 1 full 1 idle 1 pop_not_empty 1 push_not_full 0 full 0 idle 0 pop_not_empty 0 push_not_full 0 empty 0 idle 0 pop_not_empty 0 push_not_full 0 empty 0 full 0 pop_not_empty 0 push_not_full 0 empty 0 full 0 idle 0 push_not_full 0 empty 0 full 0 idle 0 pop_not_empty Preliminary In State © June 2010 Altera Corporation ...

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... Click Finish to complete the state machine definition. The state machine displays graphically in the State Editor window © June 2010 Altera Corporation shows the Actions page after you define the output ports, and action. (Figure 11–10 on page Preliminary 11– ...

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... On the File menu in the Quartus II State Machine Editor, click Exit. The fifo_controller block on your model updates with the input and output ports defined in the state machine. DSP Builder Standard Blockset User Guide Chapter 11: Using the State Machine Library Using the State Machine Editor Block Preliminary © June 2010 Altera Corporation ...

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... Figure 11–11 example. Figure 11–11. fifo_controller Block After Closing the State Machine Editor © June 2010 Altera Corporation shows the updated fifo_controller block for the FIFO design Preliminary 11–13 DSP Builder Standard Blockset User Guide ...

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... DSP Builder Standard Blockset User Guide Chapter 11: Using the State Machine Library Using the State Machine Editor Block Preliminary © June 2010 Altera Corporation ...

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... Any design that includes HDL Import, State Machine Editor or MegaCore functions requires the import directory. Integration with Source Control Systems Altera recommends that you store Quartus II archive (.qar) files rather than individual HDL files for source control purposes. To create a .qar file, follow these steps in the Quartus II software: 1 ...

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... Exporting HDL You can export the DSP Builder-generated synthesizable HDL to a Quartus II project and then use the Export tab in the Signal Compiler block to export them (Figure 12–1). DSP Builder Standard Blockset User Guide Preliminary Chapter : HDL Import © June 2010 Altera Corporation ...

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... Running this flow creates a set of source files in the export directory, including a .qip file corresponding to the top-level of your design. © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 12–3 ...

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... However, this act requires adding an additional file to the project. This additional alt_dspbuilder_package.vhd file is in the <QUARTUS_ROOTDIR>\libraries\vhdl\altera directory on a Windows computer. Migration of DSP Builder (Standard Blockset) Files to a New Location When moving DSP Builder (standard blockset) projects to a new directory or machine, you can recreate the project by transferring a minimum set of design files ...

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... The .ipx file has the following contents: <library> <path path='../../../<module name>/**/*'/> </library> © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 12–5 ...

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... DSP Builder Standard Blockset User Guide Integration of Multiple Models in a Top-Level Quartus II Project shows the design example in the Quartus II Project <path path='../../../<module name>/**/*'/> Preliminary Chapter : © June 2010 Altera Corporation ...

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... These .ipx files specify the relative path to the directory, where the .mdl file is located and tell the IP Librarian where to look for the components. Figure 12–2. Project Navigator Window in the Quartus II Software © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary ...

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... DSP Builder Standard Blockset User Guide Integration of Multiple Models in a Top-Level Quartus II Project Preliminary Chapter : © June 2010 Altera Corporation ...

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... DSP Development Board Troubleshooting ■ ■ SignalTap II Analysis Appears to Hang ■ Error if Output Block Connected to an Altera Synthesis Block ■ Warning if Input/Output Blocks Conflict with clock or aclr Ports ■ Wiring the Asynchronous Clear Signal ■ Error Issues when a Design Includes Pre-v7.1 Blocks ■ ...

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... Vendor-defined 1 You receive a message about the hostid if you are using an Altera software guard for licensing. Alternatively, if you are using a floating license: >> dos('lmutil lmdiag lmutil - Copyright (c) 1989-2006 Macrovision Europe Ltd. and/or Macrovision Corporation ...

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... Click OK. Verifying the Quartus II Path Verify that the QUARTUS_ROOTDIR environment variable points at the correct version of the Quartus II software by typing the following command in the MATLAB Command Window: !echo %QUARTUS_ROOTDIR% r © June 2010 Altera Corporation DSP Builder Standard Blockset User Guide Preliminary 13–3 ...

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... The MegaCore Functions Library Does Not Appear in Simulink The Simulink Library Browser may not display MegaCore functions library if you install DSP Builder before you install the Altera MegaCore IP Library. To fix this problem, type the following command after you instal the Altera MegaCore IP Library: alt_dspbuilder_setup_megacore r DSP Builder Standard Blockset User Guide Figure 13– ...

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... You can either disconnect and reconnect the USB cable, or switch off the board and switch it on again. You must program the board again if you power it off. Error if Output Block Connected to an Altera Synthesis Block An Output block maps to output ports in VHDL and marks the edge of the generated system ...

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... Non-synthesizable Input block. This combination functions as a temporary input terminator and you can remove them after you debug your design. DSP Builder Standard Blockset User Guide aclr has been renamed to aclr_1: (Figure 13–3). Volume 1: Introduction to DSP Preliminary Chapter : Troubleshooting Issues © June 2010 Altera Corporation ...

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... Info: IP Generator Info: stderr: Failed to find clock Info: IP Generator Info: stderr: Failed to find clock Error: IP Generator Error: Unexpected exception thrown by MDLFactory: Error: Node instance "dut" instantiates undefined entity © June 2010 Altera Corporation Guide. "TestBarrelShifter" File: <path>/mytoplevel.vhd Line: 30 Preliminary FIR ...

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... Specifying a value of 1 for an input, when fact direct feedthrough, causes Simulink to treat combinational paths as registered, and results in incorrect simulation results. DSP Builder Standard Blockset User Guide 3–27). Preliminary Chapter : Troubleshooting Issues (“Making © June 2010 Altera Corporation ...

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... DSP Builder System Not Detected in SOPC Builder SOPC Builder may not detect DSP Builder systems whose hardware has been generated using previous versions of the DSP Builder software. Altera does not guarantee backwards compatibility of these modules when you use them in SOPC Builder. ...

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... ModelSim simulation to run for one additional clock cycle (on the fastest clock) and there is no stimulus data for this extra cycle. You can ignore the error message. DSP Builder Standard Blockset User Guide manual. Preliminary Chapter : Troubleshooting Issues DSP Builder © June 2010 Altera Corporation ...

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... Section II. DSP Builder Standard Blockset Libraries 101 Innovation Drive San Jose, CA 95134 www.altera.com HB_DSPA_STD_LIB-1.0 Document Version: 1.0 Document Date: June 2010 ...

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... Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation ...

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... Revision History The following table shows the revision history for this section. Date Version June 2010 1.0 First published. © June 2010 Altera Corporation About This Section Changes Made DSP Builder Standard Blockset Libraries Preliminary ...

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... DSP Builder Standard Blockset Libraries Preliminary About This Section Revision History © June 2010 Altera Corporation ...

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... Quartus II Global Project Assignment Quartus II Pinout Assignments ■ Resource Usage ■ Signal Compiler ■ SignalTap II Logic Analyzer ■ ■ SignalTap II Node ■ Subsystem Builder ■ TestBench ■ VCD Sink © June 2010 Altera Corporation 1. AltLab Library DSP Builder Standard Blockset Libraries Preliminary ...

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... DSP Builder Standard Blockset Libraries Data Reported in Symbol Maximum number of integer bits required during simulation. Maximum or minimum value reached during simulation. Clock_Derived Preliminary Chapter 1: AltLab Library BP (Bus Probe) block. Signal Compiler (Table 1–1). blocks. © June 2010 Altera Corporation ...

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... When you specify these reset types, DSP Builder adds two extra registers to avoid metastability issues during reset removal. Table 1–3 lists the parameters for the Clock_Derived block: © June 2010 Altera Corporation Description Specify the clock period, which should be greater than 1ps but less than 2.1 ms. ...

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... Description represented by a Subsystem Builder block. Turn on to use the subsystem port names as the entity port names instead of the names of the HDL Input and HDL Output blocks. Preliminary Chapter 1: AltLab Library Display Pipeline Depth © June 2010 Altera Corporation ...

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... DSP Builder cannot find. Refer to the Quartus II documentation for information about setting the current revision of a project and how to explicitly reference the source files in your design. Browse .qpf file Click to browse for a Quartus II project file. © June 2010 Altera Corporation Description DSP Builder Standard Blockset Libraries Preliminary 1–5 ® ...

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... Table 1–7 on page 1–7 supported. DSP Builder Standard Blockset Libraries Megafunctions altsyncram lpm_abs parallel_add lpm_add_sub scfifo lpm_compare lpm_counter lists the megafunctions and LPM functions that are not Preliminary Chapter 1: AltLab Library HDL Import LPM Functions lpm_mult (Note 1) lpm_mux lpm_ram_dp © June 2010 Altera Corporation ...

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... Inferred, Simulink Fixed Point Type, Double Table 1–9 on page 1–7 Table 1–9. HDL Input Block I/O Formats (Part I/O Simulink (2), ( I1: out STD_LOGIC_VECTOR({ DOWNTO 0) [L1].[R1] © June 2010 Altera Corporation Megafunctions altmemmult lpm_and altmult_accum lpm_bustri altpll lpm_clshift altqpram lpm_constant altsqrt lpm_decode ...

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... Specify the number of bits to the right of the binary point. This parameter applies only to signed fractional buses. (Note 1) VHDL Preliminary Chapter 1: AltLab Library HDL Output Type (4) Explicit and HDL Entity blocks for block. Type (4) Implicit - Optional Explicit © June 2010 Altera Corporation ...

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... Port name Output Sync Port name Sampling Period Integer © June 2010 Altera Corporation Description Browse for a Quartus II project file ,which describes the hardware design that the HIL block uses. The clock pin name for the hardware design in the Quartus II software. ...

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... JTAG Cable and Device in chain list boxes. Click to configure the FPGA. Displays the progress of the compilation. Preliminary Chapter 1: AltLab Library HIL (Hardware in the Loop) DSP Builder Standard Blockset © June 2010 Altera Corporation ...