MA300012 Microchip Technology, MA300012 Datasheet - Page 25

• Manufacturer Part Number: MA300012
• Description: MODULE DSPIC30F SAMPLE 64QFP
• Manufacturer: Microchip Technology

Specifications of MA300012

• Module/board Type: dsPIC30F Plug-in Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: DM240001
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

8.3
The dsPIC30F devices have two reduced power
modes that can be entered through execution of the
PWRSAV instruction.
• Sleep mode: The CPU, system clock source and
• Idle mode: The CPU is disabled, but the system
These modes provide an effective way to reduce power
consumption during periods when the CPU is not is
use.
8.3.1
When the device enters Sleep mode:
• System clock source is shut down. If an on-chip
• Device current consumption is at minimum,
• Fail-Safe Clock Monitor (FSCM) does not operate
• LPRC clock continues to run in Sleep mode if the
• Low Voltage Detect circuit, if enabled, remains
• BOR circuit, if enabled, remains operative during
• WDT, if enabled, is automatically cleared prior to
• Some peripherals may continue to operate in
The processor exits (wakes up) from Sleep on one of
these events:
• Any interrupt source that is individually enabled.
• Any form of device Reset.
• A WDT time-out.
© 2005 Microchip Technology Inc.
any peripherals that operate on the system clock
source are disabled. This is the lowest power
mode of the device.
clock source continues to operate. Peripherals
continue to operate, but can optionally be
disabled.
oscillator is used, it is turned off.
provided that no I/O pin is sourcing current.
during Sleep mode because the system clock
source is disabled.
WDT is enabled.
operative during Sleep mode.
Sleep mode.
entering Sleep mode.
Sleep mode. These peripherals include I/O pins
that detect a change in the input signal, or
peripherals that use an external clock input. Any
peripheral that is operating on the system clock
source is disabled in Sleep mode.
Power-Saving Modes
SLEEP MODE
8.3.2
When the device enters Idle mode:
• CPU stops executing instructions.
• WDT is automatically cleared.
• System clock source remains active.
• Peripheral modules, by default, continue to
• Peripherals, optionally, can be shut down in Idle
• If the WDT or FSCM is enabled, the LPRC also
The processor wakes from Idle mode on these events:
• Any interrupt that is individually enabled.
• Any source of device Reset.
• A WDT Time-out.
Upon wake up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately
starting with the instruction following the PWRSAV
instruction, or the first instruction in the Interrupt
Service Routine (ISR).
operate normally from the system clock source.
mode using their ‘stop-in-idle’ control bit.
remains active.
IDLE MODE
dsPIC30F
DS70043F-page 23