AD9958/PCB Analog Devices Inc, AD9958/PCB Datasheet - Page 31

• Manufacturer Part Number: AD9958/PCB
• Description: BOARD EVALUATION FOR AD9958
• Manufacturer: Analog Devices Inc

Specifications of AD9958/PCB

• Design Resources: Low Jitter Sampling Clock Generator for High Performance ADCs Using AD9958/9858 and AD9515 (CN0109) Phase Coherent FSK Modulator (CN0186)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SERIAL I/O PORT
OVERVIEW
The AD9958 serial I/O port offers multiple configurations to
provide significant flexibility. The serial I/O port offers an SPI-
compatible mode of operation that is virtually identical to the
SPI operation found in earlier Analog Devices DDS products.
The flexibility is provided by four data pins (SDIO_0, SDIO_1,
SDIO_2, SDIO_3) that allow four programmable modes of
serial I/O operation.
Three of the four data pins (SDIO_1, SDIO_2, SDIO_3) can be
used for functions other than serial I/O port operation. These pins
can also be used to initiate a ramp-up or ramp-down (RU/RD)
of the 10-bit amplitude output scalar. In addition, SDIO_3 can
be used to provide the SYNC_I/O function that resynchronizes
the serial I/O port controller if it is out of proper sequence.
The maximum speed of the serial I/O port SCLK is 200 MHz,
but the four data pins (SDIO_0, SDIO_1, SDIO_2, SDIO_3)
can be used to further increase data throughput. The maximum
data throughput using all the SDIO pins (SDIO_0, SDIO_1,
SDIO_2, SDIO_3) is 800 Mbps.
Note that both channels share Register 0x03 to Register 0x18,
which are shown in the Register Maps and Bit Descriptions
section. This address sharing enables both DDS channels to be
written to simultaneously. For example, if a common frequency
tuning word is desired for both channels, it can be written once
through the serial I/O port to both channels. This is the default
mode of operation (all channels enabled). To enable each channel
to be independent, the two channel enable bits found in the
channel select register (CSR, Register 0x00) must be used.
There are effectively four sets or copies of addresses (Register 0x03
to Register 0x18) that the channel enable bits can access to provide
channel independence. See the Descriptions for Control Registers
section for further details of programming channels that are
common to or independent from each other. To properly read
back Register 0x03 to Register 0x18, the user must enable only
one channel enable bit at a time.
Serial operation of the AD9958 occurs at the register level,
not the byte level; that is, the controller expects that all bytes
contained in the register address are accessed. The SYNC_I/O
function can be used to abort an I/O operation, thereby allowing
fewer than all bytes to be accessed. This feature can be used to
program only a part of the addressed register. Note that only
completed bytes are affected.
There are two phases to a serial communications cycle. Phase 1
is the instruction cycle, which writes the instruction byte into
the AD9958. Each bit of the instruction byte is registered on
each corresponding rising edge of SCLK. The instruction byte
defines whether the upcoming data transfer is a write or read
operation. The instruction byte contains the serial address of
the address register.
Rev. A | Page 31 of 44
Phase 2 of the I/O cycle consists of the actual data transfer
(write/read) between the serial port controller and the serial
port buffer. The number of bytes transferred during this phase
of the communication cycle is a function of the register being
accessed. The actual number of additional SCLK rising edges
required for the data transfer and instruction byte depends on
the number of bytes in the register and the serial I/O mode of
operation.
For example, when accessing Function Register 1 (FR1), which
is three bytes wide, Phase 2 of the I/O cycle requires that three
bytes be transferred. After transferring all data bytes per the
instruction byte, the communication cycle is completed for that
register.
At the completion of a communication cycle, the AD9958 serial
port controller expects the next set of rising SCLK edges to be
the instruction byte for the next communication cycle. All data
written to the AD9958 is registered on the rising edge of SCLK.
Data is read on the falling edge of SCLK (see Figure 43 through
Figure 49). The timing specifications for Figure 41 and Figure 42
are described in Table 25.
Table 25. Timing Specifications
Parameter
t
t
t
t
t
t
t
PRE
SCLK
DSU
SCLKPWH
SCLKPWL
DHLD
DV
SDIO_x
SCLK
CS
SDO (SDIO_2)
Figure 42. Timing Diagram for Data Read for Serial I/O Port
Figure 41. Setup and Hold Timing for the Serial I/O Port
SDIO_x
SCLK
Min
1.0
5.0
2.2
2.2
1.6
0
12
t
PRE
CS
t
SCLKPWH
t
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
DSU
t
DHLD
t
SCLK
t
SCLKPWL
Description
CS setup time
Period of serial data clock
Serial data setup time
Serial data clock pulse width high
Serial data clock pulse width low
Serial data hold time
Data valid time
t
DV
AD9958