AD9461-LVDS/PCB Analog Devices Inc, AD9461-LVDS/PCB Datasheet - Page 20

• Manufacturer Part Number: AD9461-LVDS/PCB
• Description: BOARD EVAL FOR AD9461
• Manufacturer: Analog Devices Inc

Specifications of AD9461-LVDS/PCB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 130M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 3.4 Vpp
• Power (typ) @ Conditions: 2.2W @ 130MSPS
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD9461
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9461
DIGITAL OUTPUTS
LVDS Mode
The off-chip drivers on the chip can be configured to provide
LVDS-compatible output levels via Pin 3 (OUTPUT MODE).
LVDS outputs are available when OUTPUT MODE is CMOS
logic high (or AVDD1 for convenience) and a 3.74 kΩ R
resistor is placed at Pin 5 (LVDS_BIAS) to ground. Dynamic
performance, including both SFDR and SNR, maximizes when
using the AD9461 in LVDS mode; designers are encouraged to
take advantage of this mode. The AD9461 outputs include
complementary LVDS outputs for each data bit (Dx+/Dx−), the
overrange output (OR+/OR−), and the output data clock output
(DCO+/DCO−). The R
setting the output current at each output equal to a nominal
3.5 mA (11 × I
placed at the LVDS receiver inputs results in a nominal 350 mV
swing at the receiver. LVDS mode facilitates interfacing with
LVDS receivers in custom ASICs and FPGAs that have LVDS
capability for superior switching performance in noisy
environments. Single point-to-point net topologies are
recommended, with a 100 Ω termination resistor located as
close to the receiver as possible. It is recommended to keep the
trace length less than two inches and to keep differential output
trace lengths as equal as possible.
CMOS Mode
In applications that can tolerate a slight degradation in dynamic
performance, the AD9461 output drivers can be configured to
interface with 2.5 V or 3.3 V logic families by matching
DRVDD to the digital supply of the interfaced logic. CMOS
outputs are available when OUTPUT MODE is CMOS logic
low (or AGND for convenience). In this mode, the output data
bits, Dx, are single-ended CMOS, as is the overrange output,
OR+. The output clock is provided as a differential CMOS
signal, DCO+/DCO−. Lower supply voltages are recommended
to avoid coupling switching transients back to the sensitive
analog sections of the ADC. The capacitive load to the CMOS
outputs should be minimized, and each output should be
connected to a single gate through a series resistor (220 Ω) to
minimize switching transients caused by the capacitive loading.
Table 10. Digital Output Coding
Code
65,536
32,768
32,767
0
VIN+ − VIN−
Input Span = 3.4 V p-p (V)
+1.700
0
−0.000058
−1.70
R SET
). A 100 Ω differential termination resistor
SET
resistor current is multiplied on-chip,
VIN+ − VIN−
Input Span = 2 V p-p (V)
+1.000
0
−0.0000305
−1.00
SET
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Digital Output
Offset Binary (D15•••D0)
1111 1111 1111 1111
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
TIMING
The AD9461 provides latched data outputs with a pipeline delay
of 13 clock cycles. Data outputs are available one propagation
delay (t
Figure 3 for detailed timing diagrams.
OPERATIONAL MODE SELECTION
Data Format Select
The data format select (DFS) pin of the AD9461 determines
the coding format of the output data. This pin is 3.3 V CMOS
compatible, with logic high (or AVDD1, 3.3 V) selecting twos
complement and DFS logic low (AGND) selecting offset binary
format. Table 10 summarizes the output coding.
Output Mode Select
The OUPUT MODE pin controls the logic compatibility,
as well as the pinout of the digital outputs. This pin is a CMOS-
compatible input. With OUTPUT MODE = 0 (AGND), the
AD9461 outputs are CMOS compatible, and the pin assignment
for the device is as defined in Table 8. With OUTPUT MODE = 1
(AVDD1, 3.3 V), the AD9461 outputs are LVDS compatible, and
the pin assignment for the device is as defined in Table 7.
Duty Cycle Stabilizer
The DCS circuit is controlled by the DCS MODE pin; a CMOS
logic low (AGND) on DCS MODE enables the DCS, and logic
high (AVDD1, 3.3 V) disables the controller.
SFDR Enhancement
Under certain conditions, the SFDR performance of the AD9461
improves by decreasing the power of the core of the ADC. The
SFDR control pin (Pin 100) is a CMOS-compatible control pin
to optimize the configuration of the AD9461 analog front end.
Connecting SFDR to AGND optimizes SFDR performance for
applications with analog input frequencies <40 MHz or >215 MHz.
For applications with analog inputs from 40 MHz to 215 MHz,
connect this to AVDD1 for optimum SFDR performance; power
dissipation from AVDD2 decreases by ~40 mW.
PD
) after the rising edge of CLK+. Refer to Figure 2 and
Digital Output
Twos Complement (D15•••D0)
0111 1111 1111 1111
0000 0000 0000 0000
1111 1111 1111 1111
1000 0000 0000 0000