MPC555CME Freescale Semiconductor, MPC555CME Datasheet - Page 391

• Manufacturer Part Number: MPC555CME
• Description: KIT EVALUATION FOR MPC555
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC555CME

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC555
• Data Bus Width: 32 bit
• Interface Type: RS-232
• For Use With/related Products: MPC555
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

11.5.2 Associated Registers
MPC555
USER’S MANUAL
When more than one match indication occurs, the effective region is the region with
the highest priority. Priority is determined by region number; highest priority corre-
sponds to the lowest region number.
When no match occurs, the effective region is the global region. The global region has
the lowest priority.
The region attribute register also contains the region’s protection fields. The protection
field (PP) of the effective region is compared to the access attributes. If the attributes
match, the access is permitted. When the access is permitted, a U-bus access may be
generated according to the specific attribute of the effective region.
When the access by the RCPU is not permitted, the L2U module asserts a data mem-
ory storage exception to the RCPU.
For speculative load/store accesses from the RCPU to a region marked as guarded
(G bit of region attribute register is set), the L2U asks the RCPU to retry the L-bus cycle
until either the access is not speculative, or it is canceled by the RCPU.
In the case of attempted accesses to a guarded region together with any other protec-
tion violation (no access), the L2U retries the access. The L2U handles this event as
a data storage violation only when the access becomes non-speculative.
Note that access protection is active only when the PowerPC’s MSR[DR] = 1. When
MSR[DR] = 0, DMPU exceptions are disabled, all accesses are considered to be to a
guarded memory area, and no speculative accesses are allowed. In this case, if the L-
bus master [RCPU] initiates a non-SRAM cycle (access through the L2U) that is
marked speculative, the L2U asks the RCPU to retry the L-bus cycle until either the
access is not speculative, or it is canceled by the RCPU core.
Note that the programmer must not overlap the SRAM memory space with any en-
abled region. Overlapping an enabled region with SRAM memory space disables the
L2U data memory protection for that region.
If an enabled region overlaps with the L-bus space, the DMPU ignores all accesses to
addresses within the L-bus space. If an enabled region overlaps with PowerPC regis-
ter addresses, the DMPU ignores any access marked as a PowerPC access.
The following registers are used to control the DMPU of the L2U module. All the reg-
isters are special purpose registers which are accessed via the PowerPC mtspr/mf-
spr instructions. The registers are also accessed by an external master when
EMCR[CONT] = 0. See
descriptions.
/
MPC556
11.8 L2U Programming Model
L-BUS TO U-BUS INTERFACE (L2U)
Rev. 15 October 2000
for register diagrams and bit
MOTOROLA
11-5