SAB80C537-N Infineon Technologies, SAB80C537-N Datasheet - Page 28

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SAB80C537-N

Manufacturer Part Number
SAB80C537-N
Description
IC MIRCROCONTROLLER 8BIT 84PLCC
Manufacturer
Infineon Technologies
Datasheet

Specifications of SAB80C537-N

Core Processor
8051
Core Size
8-Bit
Speed
12MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Type
ROMless
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 12x8b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
84-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q1612975

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Compare
In the compare mode, the 16-bit values stored in the dedicated compare registers are
compared to the contents of the timer 2 register or the compare timer register. If the count value
in the timer registers matches one of the stored values, an appropriate output signal is
generated and an interrupt is requested. Two compare modes are provided:
Mode 0:
Mode 1:
Compare registers CM0 to CM7 use additional compare latches when operated in mode 0.
Figure 8 shows the function of these latches. The latches are implemented to prevent from loss
of compare matches which may occur when loading of the compare values is not correlated
with the timer count. The compare latches are automatically loaded from the compare registers
at every timer overflow.
Capture
This feature permits saving of the actual timer/counter contents into a selected register upon
an external event or a software write operation. Two modes are provided to latch the current
16-bit value of timer 2 registers into a dedicated capture register.
Mode 0:
Mode 1:
Reload of Timer 2
A 16-bit reload can be performed with the 16-bit CRC register, which is a concatenation of the
8-bit registers CRCL and CRCH. There are two modes from which to select:
Mode 0:
Mode 1:
Timer/Counters 0 and 1
These timer/counters are fully compatible with timer/counter 0 or 1 of the SAB 8051 and can
operate in four modes:
Mode 0:
Mode 1:
Mode 2:
Mode 3:
External inputs INT0 and INT1 can be programmed to function as a gate for timer/counters 0
and 1 to facilitate pulse width measurements.
Semiconductor Group
Upon a match the output signal changes from low to high. It goes back to low level
when the timer overflows.
The transition of the output signal can be determined by software. A timer overflow
signal doesn’t affect the compare-output.
Capture is performed in response to a transition at the corresponding port pins CC0
to CC3.
Write operation into the low-order byte of the dedicated capture register causes the
timer 2 contents to be latched into this register.
Reload is caused by a timer overflow (auto-reload).
Reload is caused in response to a negative transition at pin T2EX (P1.5), which also
can request an interrupt.
8-bit timer/counter with 32:1 prescaler
16-bit timer/counter
8-bit timer/counter with 8-bit auto reload
Timer/counter 0 is configured as one 8-bit timer; timer/counter 1 in this mode holds
its count.
27
SAB 80C517/80C537