AD5321 Analog Devices, AD5321 Datasheet

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AD5321

Manufacturer Part Number
AD5321
Description
2.5 V to 5.5 V, 120 µA, 2-Wire Interface, Voltage-Output 12-Bit DAC
Manufacturer
Analog Devices
Datasheet

Specifications of AD5321

Resolution (bits)
12bit
Dac Update Rate
125kSPS
Dac Settling Time
8µs
Max Pos Supply (v)
+5.5V
Single-supply
Yes
Dac Type
Voltage Out
Dac Input Format
I2C/Ser 2-wire,Ser

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FEATURES
AD5301: buffered voltage output 8-bit DAC
AD5311: buffered voltage output 10-bit DAC
AD5321: buffered voltage output 12-bit DAC
6-lead SOT-23 and 8-lead MSOP packages
Micropower operation: 120 μA @ 3 V
2-wire (I
Data readback capability
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 50 nA @ 3 V
Reference derived from power supply
Power-on reset to 0 V
On-chip rail-to-rail output buffer amplifier
3 power-down functions
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
2
C®-compatible) serial interface
SDA
SCL
A1*
A0
*AVAILABLE ON 8-LEAD VERSION ONLY
INTERFACE
POWER-ON
RESET
LOGIC
GND
FUNCTIONAL BLOCK DIAGRAM
REGISTER
2.5 V to 5.5 V, 120 μA, 2-Wire Interface,
DAC
Voltage-Output 8-/10-/12-Bit DACs
Figure 1.
REF
8-/10-/12-BIT
V
DAC
DD
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
GENERAL DESCRIPTION
The AD5301/AD5311/AD5321
ered, voltage-output DACs that operate from a single 2.5 V to
5.5 V supply, consuming 120 μA at 3 V. The on-chip output
amplifier allows rail-to-rail output swing with a slew rate of
0.7 V/μs. It uses a 2-wire (I
operates at clock rates up to 400 kHz. Multiple devices can share
the same bus.
The reference for the DAC is derived from the power supply
inputs and thus gives the widest dynamic output range. These
parts incorporate a power-on reset circuit, which ensures that
the DAC output powers up to 0 V and remains there until a
valid write takes place. The parts contain a power-down feature
that reduces the current consumption of the device to 50 nA at
3 V and provides software-selectable output loads while in
power-down mode.
The low power consumption in normal operation makes these
DACs ideally suited to portable battery-operated equipment. The
power consumption is 0.75 mW at 5 V and 0.36 mW at 3 V,
reducing to 1 μW in all power-down modes.
1
Protected by U.S. Patent No. 5684481.
POWER-DOWN
AD5301/AD5311/AD5321
LOGIC
PD*
BUFFER
AD5301/AD5311/AD5321
©1999–2007 Analog Devices, Inc. All rights reserved.
RESISTOR
NETWORK
2
C-compatible) serial interface that
1
are single 8-/10-/12-bit, buff-
V
OUT
www.analog.com

Related parts for AD5321

AD5321 Summary of contents

Page 1

... FEATURES AD5301: buffered voltage output 8-bit DAC AD5311: buffered voltage output 10-bit DAC AD5321: buffered voltage output 12-bit DAC 6-lead SOT-23 and 8-lead MSOP packages Micropower operation: 120 μ 2-wire (I 2 C®-compatible) serial interface Data readback capability 2 5.5 V power supply ...

Page 2

... Input Shift Register .................................................................... 14 Write Operation.......................................................................... 15 Read Operation........................................................................... 16 Power-Down Modes .................................................................. 17 Application Notes ........................................................................... 18 Using REF19x as a Power Supply ............................................. 18 Bipolar Operation Using the AD5301/AD5311/AD5321..... 18 Multiple Devices on One Bus ................................................... 18 CMOS Driven SCL and SDA Lines.......................................... 18 Power Supply Decoupling ......................................................... 19 Outline Dimensions ....................................................................... 20 Ordering Guide .......................................................................... 21 Rev Page ...

Page 3

... Rev Page AD5301/AD5311/AD5321 unless otherwise noted. MIN MAX Conditions/Comments Guaranteed monotonic by design over all codes. Guaranteed monotonic by design over all codes. Guaranteed monotonic by design over all codes. All zeros loaded to DAC, see Figure 12. ...

Page 4

... See the Terminology section specifications tested with the outputs unloaded. 4 Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); and AD5321 (Code 112 to 4000). 5 Guaranteed by design and characterization, not production tested. 6 Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns. ...

Page 5

... Capacitive load for each bus line IH MIN . Figure 2. 2-Wire Serial Interface Timing Diagram Rev Page AD5301/AD5311/AD5321 unless otherwise noted. MIN MAX = the SCL signal) in order to bridge the undefined region of SCL’ ...

Page 6

... AD5301/AD5311/AD5321 ABSOLUTE MAXIMUM RATINGS 25°C, unless otherwise noted. A Table 4. Parameter V to GND DD SCL, SDA to GND PD, A1 GND V to GND OUT Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature (T max) J SOT-23 Package Power Dissipation θ Thermal Impedance JA MSOP Package Power Dissipation θ ...

Page 7

... AD5301, two bytes for the AD5311/AD5321) during the read cycle bidirectional open-drain data line that should be pulled to the supply with an external pull-up resistor. If not used in readback mode, SDA may be CMOS/TTL driven ...

Page 8

... DAC register. Ideally, the output should The zero-code error of the AD5301/AD5311/ AD5321 is always positive because the output of the DAC cannot go below 0 V, due to a combination of the offset errors in the DAC and output amplifier expressed in millivolts, see Figure 12 ...

Page 9

... CODE Figure 6. AD5311 Typical INL Plot 25° –4 –8 –12 0 1000 2000 CODE Figure 7. AD5321 Typical INL Plot 0.3 0.2 0.1 –0.1 –0.2 –0.3 200 255 0.6 0.4 0.2 –0.2 –0.4 –0.6 800 1023 1.0 0.5 –0.5 –1.0 3000 4095 Rev Page ...

Page 10

... AD5301/AD5311/AD5321 1. 0.75 0.50 MAX INL MAX DNL 0.25 0 –0.25 MIN DNL –0.50 MIN INL –0.75 –1.00 – TEMPERATURE (°C) Figure 11. AD5301 INL Error and DNL Error vs. Temperature ZERO CODE –2 –4 FULL SCALE –6 –8 –10 –40 –20 ...

Page 11

... Figure 18. Supply Current vs. Logic Input Voltage for SDA and SCL Voltage Increasing and Decreasing 1 +25°C +105°C 4.7 5.2 Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Charge) INCREASING CH1 CH2 4.0 5.0 Rev Page AD5301/AD5311/AD5321 25°C A LOAD = 2kΩ AND 200pF TO GND V OUT CH1 1V, TIME BASE = 5µs/DIV T = 25° ...

Page 12

... AD5301/AD5311/AD5321 T = 25° OUT CH1 CH2 CLK CH1 1V, CH2 5V, TIME BASE = 1µs/DIV Figure 21. Exiting Power-Down to Midscale 2.50 2.49 2.48 2.47 1µs/DIV Figure 22. Major-Code Transition 2.440 2.445 2.450 2.455 Rev Page 1ns/DIV Figure 23. Digital Feedthrough ...

Page 13

... Figure 14. The slew rate is 0.7 V/μs with a half-scale settling time to ±0.5 LSB (at 8 bits μs with the output unloaded. POWER-ON RESET The AD5301/AD5311/AD5321 are provided with a power-on AMPLIFIER reset function, ensuring that they power defined state. V OUT The DAC register is filled with zeros and remains so until a valid write sequence is made to the device ...

Page 14

... The master then brings the SDA line low before the 10 clock pulse and then high during the 10 establish a stop condition. In the case of the AD5301/AD5311/AD5321, a write operation contains two bytes whereas a read operation may contain one or two bytes. See Figure 29 to Figure 34 for a graphical explanation of the serial interface ...

Page 15

... WRITE OPERATION When writing to the AD5301/AD5311/AD5321 DACs, the user must begin with an address byte, after which the DAC acknowledges that it is prepared to receive data by pulling SCL SDA START ADDRESS BYTE COND BY MASTER SCL SDA LEAST SIGNIFICANT CONTROL BYTE *THIS BIT MUST THE 6-LEAD SOT-23 VERSION. ...

Page 16

... BIT MUST THE 6-LEAD SOT-23 VERSION. the eight data bits in the DAC register. However, in the case of the AD5311 and AD5321, the readback consists of two bytes that contain both the data and the power-down mode bits. The read operations for the three DACs are shown in Figure 32 to Figure 34 ...

Page 17

... POWER-DOWN MODES The AD5301/AD5311/AD5321 have very low power consump- tion, dissipating typically 0.36 mW with supply and 0.75 mW with supply. Power consumption can be further reduced when the DAC is not in use by putting it into one of three power-down modes, which are selected by Bit 13 and Bit 12 (PD1 and PD0) of the control word ...

Page 18

... AD5301/AD5311/AD5321 APPLICATIONS NOTES USING REF19x AS A POWER SUPPLY Because the supply current required by the AD5301/AD5311/ AD5321 is extremely low, the user has an alternative option to employ a REF195 voltage reference (for reference (for supply the required voltage to the part (see Figure 36). ...

Page 19

... AD5301 a ceramic 0.1 μF capacitor provides a sufficient low impedance path to ground at high frequencies. The power supply lines of the AD5301/AD5311/AD5321 should use as large a trace as possible to provide low impedance paths. A ground line routed between the SDA and SCL lines helps reduce crosstalk between them. This is not required on a multilayer board as there is a ground plane layer, but separating the lines helps ...

Page 20

... AD5301/AD5311/AD5321 OUTLINE DIMENSIONS INDICATOR 0.15 MAX 2.90 BSC 2.80 BSC 1.60 BSC PIN 1 0.95 BSC 1.90 1.30 BSC 1.15 0.90 1.45 MAX 0.22 0.08 0.50 SEATING 0.30 PLANE COMPLIANT TO JEDEC STANDARDS MO-178-AB Figure 39. 6-Lead Small Outline Transistor Package [SOT-23] (RJ-6) Dimensions shown in millimeters 3.20 3.00 2.80 5. 3.20 4.90 3.00 4.65 2. PIN 1 0.65 BSC 0.95 0.85 1.10 MAX 0.75 8° 0.15 0.38 0.23 0° 0.00 0.22 0.08 SEATING COPLANARITY PLANE 0.10 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 40 ...

Page 21

... AD5321BRM AD5321BRM-REEL AD5321BRM-REEL7 1 AD5321BRMZ 1 AD5321BRMZ-REEL 1 AD5321BRMZ-REEL7 AD5321BRT-500RL7 AD5321BRT-REEL AD5321BRT-REEL7 1 AD5321BRTZ-500RL7 AD5321BRTZ-REEL 1 1 AD5321BRTZ-REEL7 RoHS Compliant Part; # denotes RoHS Compliant product, may be top or bottom marked. Temperature Range Package Description –40°C to +105°C 8-Lead MSOP –40°C to +105°C 8-Lead MSOP – ...

Page 22

... AD5301/AD5311/AD5321 NOTES Rev Page ...

Page 23

... NOTES AD5301/AD5311/AD5321 Rev Page ...

Page 24

... AD5301/AD5311/AD5321 NOTES Purchase of licensed components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I 2 Rights to use these components system, provided that the system conforms to the I ©1999–2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners ...

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