EP1C4 ALTERA [Altera Corporation], EP1C4 Datasheet

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This section provides designers with the data sheet specifications for Cyclone architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Cyclone devices. This section contains the following ...

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Revision History Section I–2 Preliminary Cyclone Device Handbook, Volume 1 Altera Corporation ...

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C51001-1.4 Introduction The Cyclone 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phase- locked loops (PLLs) for clocking and a dedicated double data rate (DDR) ...

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... Support for external memory, including DDR SDRAM (133 MHz), FCRAM, and single data rate (SDR) SDRAM Support for multiple intellectual property (IP) cores, including ® ® Altera MegaCore functions and Altera Megafunctions Partners Program (AMPP ) megafunctions. SM EP1C3 EP1C4 2,910 4,000 13 17 59,904 78,336 1 2 104 301 EP1C6 ...

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... Cyclone devices are available in quad flat pack (QFP) and space-saving FineLine Table 1–2. Cyclone Package Options & I/O Pin Counts 100-Pin TQFP 144-Pin TQFP Device (1) EP1C3 65 EP1C4 EP1C6 EP1C12 EP1C20 Notes to Table 1–2: (1) TQFP: thin quad flat pack. PQFP: plastic quad flat pack. ...

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Cyclone Device Handbook, Volume 1 Table 1–3. Cyclone QFP & FineLine BGA Package Sizes 100-Pin Dimension TQFP Pitch (mm) 0.5 2 256 Area (mm ) Length × width 16 × 16 (mm × mm) Document Table 1–4 Revision History Table ...

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C51002-1.5 Functional Cyclone architecture to implement custom logic. Column and row interconnects Description of varying speeds provide signal interconnects between LABs and embedded memory blocks. The logic array consists of LABs, with 10 LEs in each LAB ...

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... Figure 2–1. Cyclone EP1C12 Device Block Diagram IOEs Logic Array PLL M4K Blocks The number of M4K RAM blocks, PLLs, rows, and columns vary per device. Table 2–1. Cyclone Device Resources Device Columns EP1C3 1 EP1C4 1 EP1C6 1 EP1C12 2 EP1C20 2 2–2 Preliminary EP1C12 Device Table 2–1 lists the resources available in each Cyclone device ...

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Logic Array Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local interconnect, look-up table (LUT) chain, and register chain connection Blocks lines. The local interconnect transfers signals between LEs in the same LAB. LUT chain ...

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Cyclone Device Handbook, Volume 1 performance and flexibility. Each LE can drive 30 other LEs through fast local and direct link interconnects. connection. Figure 2–3. Direct Link Connection Direct link interconnect from left LAB, M4K memory block, PLL, or IOE ...

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With the LAB-wide addnsub control signal, a single LE can implement a one-bit adder and subtractor. This saves LE resources and improves performance for logic functions such as DSP correlators and signed multipliers that alternate between addition and subtraction depending ...

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Cyclone Device Handbook, Volume 1 Figure 2–5. Cyclone LE LAB Carry-In Carry-In1 addnsub Carry-In0 data1 data2 Look-Up data3 Table (LUT) data4 labclr1 labclr2 Asynchronous labpre/aload Clear/Preset/ Load Logic Chip-Wide Reset Clock & Clock Enable Select labclk1 labclk2 labclkena1 labclkena2 Each ...

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Another special packing mode allows the register output to feed back into the LUT of the same LE so that the register is packed with its own fan-out LUT. This provides another mechanism for improved fitting. The LE can ...

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Cyclone Device Handbook, Volume 1 preset/load, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all LE modes. The addnsub control signal is allowed in arithmetic mode. The Quartus II software, in ...

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Dynamic Arithmetic Mode The dynamic arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators dynamic arithmetic mode uses four 2-input LUTs configurable as a dynamic adder/subtractor. The first two 2-input LUTs compute ...

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Cyclone Device Handbook, Volume 1 Figure 2– Dynamic Arithmetic Mode LAB Carry-In Carry-In0 Carry-In1 addnsub (LAB Wide) (1) data1 LUT data2 data3 LUT LUT LUT Carry-Out0 Note to Figure 2–7: The addnsub signal is tied to the carry ...

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Figure 2–8 adder. One portion of the LUT generates the sum of two bits using the input signals and the appropriate carry-in bit; the sum is routed to the output of the LE. The register can be bypassed for simple ...

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Cyclone Device Handbook, Volume 1 The Quartus II Compiler automatically creates carry chain logic during design processing, or you can create it manually during design entry. Parameterized functions such as LPM functions automatically take advantage of carry chains for the ...

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Dedicated row interconnects route signals to and from LABs, PLLs, and M4K memory blocks within the same row. These row resources include: ■ ■ The direct link interconnect allows an LAB or M4K memory block ...

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Cyclone Device Handbook, Volume 1 Figure 2–9. R4 Interconnect Connections R4 Interconnect Driving Left Notes to Figure 2–9: (1) C4 interconnects can drive R4 interconnects. (2) This pattern is repeated for every LAB in the LAB row. The column interconnect ...

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Figure 2–10. LUT Chain & Register Chain Interconnects The C4 interconnects span four LABs or M4K blocks up or down from a source LAB. Every LAB has its own set of C4 interconnects to drive either up or down. LAB ...

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Cyclone Device Handbook, Volume 1 Figure 2–11. C4 Interconnect Connections Row Interconnect Adjacent LAB can drive onto neighboring LAB's C4 interconnect Note to Figure 2–11: (1) Each C4 interconnect can drive either up or down four rows. 2–16 Preliminary Note ...

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All embedded blocks communicate with the logic array similar to LAB- to-LAB interfaces. Each block (i.e., M4K memory or PLL) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also ...

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Cyclone Device Handbook, Volume 1 Embedded The Cyclone embedded memory consists of columns of M4K memory blocks. EP1C3 and EP1C6 devices have one column of M4K blocks, while Memory EP1C12 and EP1C20 devices have two columns (see page 1–2 various ...

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In addition to true dual-port memory, the M4K memory blocks support simple dual-port and single-port RAM. Simple dual-port memory supports a simultaneous read and write. Single-port memory supports non-simultaneous reads and writes. M4K RAM memory port configurations. Figure 2–13. Simple ...

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Cyclone Device Handbook, Volume 1 signal. The output registers can be bypassed. Pseudo-asynchronous reading is possible in the simple dual-port mode of M4K blocks by clocking the read enable and read address registers on the negative clock edge and bypassing ...

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M4K RAM block (×36). To create larger shift registers, multiple memory blocks are cascaded together. Data is written into each address ...

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Cyclone Device Handbook, Volume 1 is not available in the true dual-port mode. Mixed-width configurations are also possible, allowing different read and write widths. and Table 2–3. M4K RAM Block Configurations (Simple Dual-Port) Read Port 4K × × ...

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Byte Enables M4K blocks support byte writes when the write port has a data width of 16, 18, 32 bits. The byte enables allow the input data to be masked so the device can write to specific bytes. ...

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Cyclone Device Handbook, Volume 1 Figure 2–15. M4K RAM Block Control Signals Dedicated 6 LAB Row Clocks Local Interconnect Local Interconnect Local Interconnect Local Interconnect Local Interconnect clock_a Figure 2–16. M4K RAM Block LAB Row Interface C4 Interconnects 10 Direct ...

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Independent Clock Mode The M4K memory blocks implement independent clock mode for true dual-port memory. In this mode, a separate clock is available for each port (ports A and B). Clock A controls all registers on the port A side, ...

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Cyclone Device Handbook, Volume 1 Figure 2–18. Input/Output Clock Mode in True Dual-Port Mode 6 LAB Row Clocks 6 data [ ] ENA byteena [ ] ENA address [ ] ENA ...

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Figure 2–19. Input/Output Clock Mode in Simple Dual-Port Mode 6 LAB Row Clocks 6 data[ ] address[ ] byteena[ ] wraddress[ ] rden wren outclken inclken inclock outclock Notes to Figure 2–19: (1) All registers shown except the rden register ...

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Cyclone Device Handbook, Volume 1 Read/Write Clock Mode The M4K memory blocks implement read/write clock mode for simple dual-port memory. You can use up to two clocks in this mode. The write clock controls the block's data inputs, wraddress, and ...

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Single-Port Mode The M4K memory blocks also support single-port mode, used when simultaneous reads and writes are not required. See M4K memory block can support up to two single-port mode RAM blocks if each RAM block is less than or ...

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Cyclone Device Handbook, Volume 1 The eight global clock lines in the global clock network drive throughout the entire device. The global clock network can provide clocks for all resources within the device ⎯ IOEs, LEs, and memory blocks. The ...

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Dual-Purpose Clock Pins Each Cyclone device except the EP1C3 device has eight dual-purpose clock pins, DPCLK[7..0] (two on each I/O bank). EP1C3 devices have five DPCLK pins in the 100-pin TQFP package. These dual-purpose pins can connect to the global ...

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Cyclone Device Handbook, Volume 1 Figure 2–24. I/O Clock Regions 6 Cyclone Logic Array LAB Row Clocks labclk[5..0] 6 LAB Row Clocks labclk[5..0] 6 LAB Row Clocks labclk[5.. PLLs Cyclone PLLs provide general-purpose clocking with clock multiplication and ...

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Table 2–6 a Cyclone PLL. Table 2–6. Cyclone PLL Features Clock multiplication and division Phase shift Programmable duty cycle Number of internal clock outputs Number of external clock outputs Notes to (1) (2) (3) (4) Figure 2–25. Cyclone PLL Note ...

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Cyclone Device Handbook, Volume 1 Figure 2–26 Figure 2–26. Cyclone PLL Global Clock Connections CLK0 PLL1 CLK1 (1) PLL1_OUT (3), (4) Notes to Figure 2–26: PLL 1 supports one single-ended or LVDS input via pins CLK0 and CLK1. (1) PLL2 ...

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Table 2–7. Global Clock Network Sources (Part Source GCLK0 (3) Dual-Purpose DPCLK0 Clock Pins (3) DPCLK1 v DPCLK2 DPCLK3 DPCLK4 (3) DPCLK5 DPCLK6 DPCLK7 Notes to Table 2–7: (1) EP1C3 devices only have one PLL (PLL 1). ...

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Cyclone Device Handbook, Volume 1 External Clock Inputs Each PLL supports single-ended or differential inputs for source- synchronous receivers or for general-purpose use. The dedicated clock pins (CLK[3..0]) feed the PLL inputs. These dual-purpose pins can also act as LVDS ...

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The EP1C6 device in the 144-pin TQFP package only supports dedicated clock outputs from PLL 1. Clock Feedback Cyclone PLLs have three modes for multiplication and/or phase shifting: ■ ■ ■ Phase Shifting ...

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Cyclone Device Handbook, Volume 1 Programmable Duty Cycle The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on each PLL post-scale counter (g0, g1, e). The duty cycle setting is ...

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I/O Structure IOEs support many features, including: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Cyclone device IOEs contain a bidirectional I/O buffer and three registers for complete embedded bidirectional single data rate transfer. Figure 2–27 ...

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Cyclone Device Handbook, Volume 1 Figure 2–27. Cyclone IOE Structure Note to (1) The IOEs are located in I/O blocks around the periphery of the Cyclone device. There are up to three IOEs per row I/O block and up to ...

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Figure 2–28. Row I/O Block Connection to the Interconnect R4 Interconnects LAB Direct Link Interconnect to Adjacent LAB LAB Local Interconnect Notes to Figure 2–28: The 21 data and control signals consist of three data out lines, io_dataout[2..0], three output ...

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Cyclone Device Handbook, Volume 1 Figure 2–29. Column I/O Block Connection to the Interconnect 21 Data & Control Signals from Logic Array (1) I/O Block Local Interconnect R4 Interconnects LAB LAB Local Interconnect Notes to Figure 2–29: The 21 data ...

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The pin's datain signals can drive the logic array. The logic array drives the control and data signals, providing a flexible routing resource. The row or column IOE clocks, io_clk[5..0], provide a dedicated routing resource for low-skew, high-speed clocks. The ...

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Cyclone Device Handbook, Volume 1 Figure 2–31. Control Signal Selection per IOE Dedicated I/O Clock [5..0] io_coe Local Interconnect io_csclr Local Interconnect io_caclr Local Interconnect io_cce_out Local Interconnect io_cce_in Local Interconnect io_cclk Local Interconnect In normal bidirectional operation, you can ...

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Figure 2–32. Cyclone IOE in Bidirectional I/O Configuration ioe_clk[5..0] Column or Row Interconect OE clkout ce_out aclr/prn Chip-Wide Reset sclr/preset comb_datain data_in clkin ce_in The Cyclone device IOE includes programmable delays to ensure zero hold times, minimize setup times, or ...

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Cyclone Device Handbook, Volume 1 to automatically minimize setup time while providing a zero hold time. Programmable delays can increase the register-to-pin delays for output registers. Table 2–9. Cyclone Programmable Delay Chain Input pin to logic array delay Input pin ...

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... Each DQ group consists of one DQS pin, eight DQ pins, and one DM pin. Table 2–10 Table 2–10. DQ Pin Groups (Part Device EP1C3 EP1C4 Altera Corporation January 2007 Note (1) DQ Pins DQS Pin shows the number of DQ pin groups per device. Number of × ...

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Cyclone Device Handbook, Volume 1 Table 2–10. DQ Pin Groups (Part Device EP1C6 EP1C12 EP1C20 Note to (1) A programmable delay chain on each DQS pin allows for either a 90° phase shift (for DDR SDRAM), or ...

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Figure 2–34. DDR SDRAM & FCRAM Interfacing Register Output Register Register V CC Output LE Register GND PLL Phase Shifted -90˚ Programmable Drive Strength The output buffer for each Cyclone device I/O pin has ...

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Cyclone Device Handbook, Volume 1 of the standard. Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot. possible settings for the I/O standards with drive strength control. Table 2–11. Programmable Drive Strength LVTTL (3.3 ...

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Slew-Rate Control The output buffer for each Cyclone device I/O pin has a programmable output slew-rate control that can be configured for low noise or high- speed performance. A faster slew rate provides high-speed transitions for high-performance systems. However, these ...

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Cyclone Device Handbook, Volume 1 Advanced I/O Standard Support Cyclone device IOEs support the following I/O standards: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Table 2–12 Table 2–12. Cyclone I/O Standards I/O Standard 3.3-V LVTTL/LVCMOS Single-ended 2.5-V ...

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DM pins to support a DDR SDRAM or FCRAM interface. I/O bank 1 can also support a DDR SDRAM or FCRAM interface, however, the configuration input pins in I/O bank 1 must operate at 2.5 V. I/O bank 3 ...

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... These pins do not contain dedicated serialization or deserialization circuitry; therefore, internal logic performs serialization and deserialization functions. Table 2–13 device density. Table 2–13. Cyclone Device LVDS Channels EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Note to (1) MultiVolt I/O Interface The Cyclone architecture supports the MultiVolt I/O interface feature, which allows Cyclone devices in all packages to interface with systems of different supply voltages ...

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The Cyclone V supply. If the V and 3.3-V tolerant. The V 2.5-V, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply (i.e., when V ...

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Cyclone Device Handbook, Volume 1 Document Table 2–15 Revision History Table 2–15. Document Revision History Date & Document Version January 2007 ● Added document revision history. v1.5 ● Updated Figures August 2005 Minor updates. v1.4 February 2005 ● Updated JTAG ...

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C51003-1.3 IEEE Std. 1149.1 All Cyclone IEEE Std. 1149.1a-1990 specification. JTAG boundary-scan testing can be (JTAG) Boundary performed either before or after, but not during configuration. Cyclone Scan Support devices can also use the JTAG port for configuration together with ...

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Cyclone Device Handbook, Volume 1 Table 3–1. Cyclone JTAG Instructions (Part JTAG Instruction Instruction Code USERCODE 00 0000 0111 IDCODE 00 0000 0110 HIGHZ (1) 00 0000 1011 CLAMP (1) 00 0000 1010 ICR instructions PULSE_NCONFIG 00 ...

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... The most significant bit (MSB the left. The IDCODE’s least significant bit (LSB) is always 1. (2) Altera Corporation January 2007 IEEE Std. 1149.1 (JTAG) Boundary Scan Support Device EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 IDCODE (32 bits) (1) Manufacturer Identity Part Number (16 Bits) ...

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Cyclone Device Handbook, Volume 1 Figure 3–1 Figure 3–1. Cyclone JTAG Waveforms Signal Captured Signal Driven Table 3–4 devices. Table 3–4. Cyclone JTAG Timing Parameters & Values Symbol ...

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For more information on JTAG, see the following documents: ■ ■ SignalTap II Cyclone devices feature the SignalTap II embedded logic analyzer, which monitors design operation over a period of time through the IEEE Embedded Logic Std. 1149.1 ...

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Cyclone Device Handbook, Volume 1 Operating Modes The Cyclone architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called ...

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Multiple Cyclone devices can be configured in any of the three configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device. Table 3–5. Data Sources for Configuration Active serial Passive serial (PS) JTAG ...

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Cyclone Device Handbook, Volume 1 3–8 Preliminary Altera Corporation January 2007 ...

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C51004-1.6 Operating Cyclone extended temperature grades. However, industrial-grade and extended- Conditions temperature-grade devices may have limited speed-grade availability. Tables 4–1 ratings, recommended operating conditions, DC operating conditions, and capacitance for Cyclone devices. Table 4–1. Cyclone Device Absolute Maximum Ratings Symbol ...

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... For extended- –40 temperature use Note (6) Conditions Minimum (8) – ( – EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 3 CCI0 2 CCI0 1 CCI0 ...

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Table 4–4. LVTTL Specifications (Part Symbol Parameter V High-level output voltage OH V Low-level output voltage OL Table 4–5. LVCMOS Specifications Symbol Parameter V Output supply voltage CCIO V High-level input voltage IH V Low-level input voltage ...

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Cyclone Device Handbook, Volume 1 Table 4–7. 1.8-V I/O Specifications Symbol Parameter V Output supply voltage CCIO V High-level input voltage Low-level input voltage IL V High-level output voltage OH V Low-level output voltage OL Table 4–8. ...

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Table 4–10. 3.3-V PCI Specifications Symbol Parameter V Output supply voltage CCIO V High-level input voltage IH V Low-level input voltage IL V High-level output voltage OH V Low-level output voltage OL Table 4–11. SSTL-2 Class I Specifications Symbol Parameter ...

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Cyclone Device Handbook, Volume 1 Table 4–13. SSTL-3 Class I Specifications Symbol Parameter V Output supply voltage CCIO V Termination voltage TT V Reference voltage REF V High-level input voltage IH V Low-level input voltage IL V High-level output voltage ...

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Table 4–16. Cyclone Device Capacitance Symbol C Input capacitance for user I/O pin IO C Input capacitance for dual-purpose LVDS/user I/O pin LVDS C Input capacitance for dual-purpose V VREF C Input capacitance for dual-purpose DPCLK C Input capacitance for ...

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... Cyclone devices require a certain amount of power-up current to successfully power up because of the nature of the leading-edge process on which they are fabricated. current required to power up a Cyclone device. Table 4–17. Cyclone Maximum Power-Up Current (I Device Commercial Specification EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Notes to Table 4–17: (1) The Cyclone devices (except for the EP1C20 device) meet the power up specification for Mini PCI ...

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... Table 4–18. Cyclone Device Timing Model Status Altera Corporation January 2007 Table 4–17. Altera recommends using the consumption and then select power supplies or CCINT ® II software issues an informational message during the design Device Preliminary EP1C3 EP1C4 EP1C6 EP1C12 EP1C20 Timing Model Table 4–18 shows the Final 4– ...

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Cyclone Device Handbook, Volume 1 Performance The maximum internal logic array clock tree frequency is limited to the specifications shown in Table 4–19. Clock Tree Maximum Performance Specification Parameter Definition Clock tree Maximum frequency f that the clock tree M ...

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Table 4–20. Cyclone Device Performance Resource Design Size & Used Function M4K RAM 128 × 36 bit Single port memory RAM 128 × 36 bit Simple block dual-port mode RAM 256 × 18 bit True dual- port mode FIFO 128 ...

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Cyclone Device Handbook, Volume 1 Table 4–22. IOE Internal Timing Microparameter Descriptions PIN2COMBOUT_R t PIN2COMBOUT_C t COMBIN2PIN_R t COMBIN2PIN_C t CLR t PRE t CLKHL Table 4–23. M4K Block Internal Timing Microparameter Descriptions ...

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Table 4–24. Routing Delay Internal Timing Microparameter Descriptions LOCAL Figure 4–1 shown in Figure 4–1. Dual-Port RAM Timing Microparameter Waveform wrclock t WEREH wren an-1 an wraddress t DATAH din-1 data-in din t DATASU rdclock ...

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Cyclone Device Handbook, Volume 1 Internal timing parameters are specified on a speed grade basis independent of device density. internal timing microparameters for LEs, IOEs, TriMatrix memory structures, DSP blocks, and MultiTrack interconnects. Table 4–25. LE Internal Timing Microparameters t ...

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Table 4–27. M4K Block Internal Timing Microparameters t M4KRC t M4KWC t M4KWERESU t M4KWEREH t M4KBESU t M4KBEH t M4KDATAASU t M4KDATAAH t M4KADDRASU t M4KADDRAH t M4KDATABSU t M4KDATABH t M4KADDRBSU t M4KADDRBH t M4KDATACO1 t M4KDATACO2 t ...

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Cyclone Device Handbook, Volume 1 Figure 4–2. External Timing in Cyclone Devices All external I/O timing parameters shown are for 3.3-V LVTTL I/O standard with the maximum current strength and fast slew rate. For external I/O timing using standards other ...

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Table 4–29. Cyclone Global Clock External I/O Timing Parameters Symbol t Clock-to-output delay output or bidirectional pin using IOE output register with global clock enhanced PLL with default phase setting Notes to ...

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... Table 4–33. EP1C4 Row Pin Global Clock External I/O Timing Parameters Symbol ...

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Tables 4–34 and row pins for EP1C6 devices. Table 4–34. EP1C6 Column Pin Global Clock External I/O Timing Parameters Symbol ...

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Cyclone Device Handbook, Volume 1 Table 4–36. EP1C12 Column Pin Global Clock External I/O Timing Parameters (Part Symbol Table 4–37. EP1C12 ...

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Table 4–39. EP1C20 Row Pin Global Clock External I/O Timing Parameters Symbol ...

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Cyclone Device Handbook, Volume 1 Table 4–40. Cyclone I/O Standard Column Pin Input Delay Adders (Part Speed Grade I/O Standard Min SSTL-2 class II LVDS Table 4–41. Cyclone I/O Standard Row Pin Input Delay Adders -6 ...

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Table 4–42. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part Speed Grade Standard Min 2.5-V LVTTL 1.8-V LVTTL ...

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Cyclone Device Handbook, Volume 1 Table 4–43. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Row Pins (Part Speed Grade Standard Min 1.8-V LVTTL 1.5-V LVTTL 2 ...

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Table 4–44. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Column Pins (Part Speed Grade I/O Standard Min 1.5-V LVTTL SSTL-3 class I SSTL-3 class II SSTL-2 ...

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Cyclone Device Handbook, Volume 1 Table 4–45. Cyclone I/O Standard Output Delay Adders for Slow Slew Rate on Row Pins (Part Speed Grade I/O Standard Min SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 ...

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Table 4–47. Cyclone IOE Programmable Delays on Row Pins Parameter Setting Decrease input delay to Off internal cells Small Medium Large On Decrease input delay to input Off register On Increase delay to output pin Off On Note to Table ...

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Cyclone Device Handbook, Volume 1 Table 4–49. Cyclone Maximum Input Clock Rate for Row Pins LVTTL 2.5 V 1.8 V 1.5 V LVCMOS SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II 3.3-V PCI LVDS Note to ...

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Table 4–51. Cyclone Maximum Output Clock Rate for Row Pins LVTTL 2.5 V 1.8 V 1.5 V LVCMOS SSTL-3 class I SSTL-3 class II SSTL-2 class I SSTL-2 class II 3.3-V PCI LVDS Note to (1) PLL Timing Table 4–52 ...

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Cyclone Device Handbook, Volume 1 Table 4–52. Cyclone PLL Specifications (Part Symbol f (to global clock) PLL output frequency OUT (-6 speed grade) PLL output frequency (-7 speed grade) PLL output frequency (-8 speed grade) t DUTY ...

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Document Table 4–53 Revision History Table 4–53. Document Revision History Date & Document Version January 2007 ● Added document revision history. v1.6 ● Added new row for V ● Updated R CONF ● Added new Note (12) Table 4–7 and ...

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Cyclone Device Handbook, Volume 1 4–32 Preliminary Altera Corporation January 2007 ...

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C51005-1.3 Software Cyclone software, which provides a comprehensive environment for system-on-a- programmable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis, SignalTap and device configuration. Refer to ...

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Cyclone Device Handbook, Volume 1 Document Table 5–1 Revision History Table 5–1. Document Revision History Date & Document Version January 2007 Added document revision history. v1.3 August 2005 Minor updates. v1.2 February 2005 Updated Figure 5-1. v1.1 May 2003 v1.0 ...