ICS8705 ICST [Integrated Circuit Systems], ICS8705 Datasheet
ICS8705
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ICS8705 Summary of contents
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... The single ended CLK0 input accepts LVCMOS or LVTTL input levels.The ICS8705 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz ...
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... www.icst.com/products/hiperclocks.html 2 ICS8705 - -LVCMOS/LVTTL IFFERENTIAL LOCK ENERATOR ...
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... www.icst.com/products/hiperclocks.html 3 ICS8705 - -LVCMOS/LVTTL LOCK ENERATOR ...
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... www.icst.com/products/hiperclocks.html 4 ICS8705 - -LVCMOS/LVTTL IFFERENTIAL LOCK ENERATOR 70° ...
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... www.icst.com/products/hiperclocks.html 5 ICS8705 - -LVCMOS/LVTTL IFFERENTIAL LOCK ENERATOR 70° ...
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... www.icst.com/products/hiperclocks.html 6 ICS8705 - -LVCMOS/LVTTL IFFERENTIAL LOCK ENERATOR 70° ...
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... www.icst.com/products/hiperclocks.html 7 ICS8705 - -LVCMOS/LVTTL IFFERENTIAL LOCK ENERATOR 70° ...
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... C 2.5V C /2.5V O IRCUIT ORE Qx V CMR UTPUT KEW V DDO 2 20% t ➤ cycle n+1 Clock Outputs cycle n UTPUT ISE www.icst.com/products/hiperclocks.html 8 ICS8705 - -LVCMOS/LVTTL IFFERENTIAL LOCK ENERATOR NFORMATION SCOPE UTPUT OAD EST IRCUIT V DDO 2 V DDO 2 t sk(o) 80% 80% 20 ...
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... UTPUT UTY YCLE ULSE IDTH ERIOD 8705BY ERO ELAY IFFERENTIAL CLK0 nCLK1 DDO CLK1 Q0:Q7 is the average ➤ mean P D ROPAGATION ELAY V DDO 2 www.icst.com/products/hiperclocks.html 9 ICS8705 - -LVCMOS/LVTTL LOCK ENERATOR V DDO 2 ➤ REV. G JUNE 16, 2004 ...
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... UPPLY ILTERING ECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS8705 provides sepa- rate power supplies to isolate any high switching noise from the outputs to the internal PLL. V should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin ...
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... HiPerClockS Input D F 3B. H NPUT RIVEN BY IGURE RIVER 3.3V 3.3V LVDS_Driv er CLK nCLK HiPerClockS Input 3D. H NPUT RIVEN BY IGURE www.icst.com/products/hiperclocks.html 11 ICS8705 - -LVCMOS/LVTTL IFFERENTIAL LOCK ENERATOR 3. Ohm CLK Ohm nCLK HiPerClockS Input CLK/ CLK I D ...
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... Circuit Systems, Inc AYOUT UIDELINE The schematic of the ICS8705 layout example is shown in Figure 4A. The ICS8705 recommended PCB board layout for this example is shown in Figure 4B. This layout example is used as a general guideline. The layout in the actual system will VDD Ohm ...
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... The series termination resistors should be located as close to the driver pins as possible. 50 Ohm Trace C16 C11 Ohm Trace 4B. PCB IGURE OARD AYOUT OR www.icst.com/products/hiperclocks.html 13 ICS8705 - -LVCMOS/LVTTL IFFERENTIAL LOCK ENERATOR GND VDD VIA Other signals C6 C5 ICS8705 REV. G JUNE 16, 2004 ...
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... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs RANSISTOR OUNT The transistor count for ICS8705 is: 3126 8705BY ERO ELAY ...
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... ° www.icst.com/products/hiperclocks.html 15 ICS8705 - -LVCMOS/LVTTL IFFERENTIAL LOCK ENERATOR ° REV. G JUNE 16, 2004 ...
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... L " " " " www.icst.com/products/hiperclocks.html 16 ICS8705 - -LVCMOS/LVTTL IFFERENTIAL LOCK ENERATOR ° ...
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... " www.icst.com/products/hiperclocks.html 17 ICS8705 - -LVCMOS/LVTTL IFFERENTIAL LOCK ENERATOR ...