ICS95V857 IDT [Integrated Device Technology], ICS95V857 Datasheet
ICS95V857
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ICS95V857 Summary of contents
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... FB_INT FB_INC CLK_INC CLK_INT ICS95V857 Pin Configuration GND 1 48 CLKC0 2 47 CLKT0 3 46 VDD 4 45 CLKT1 5 44 CLKC1 6 43 GND 7 42 GND 8 41 CLKC2 9 40 CLKT2 10 ...
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... NC NC CLKC2 NC NC VDD AVDD NC NC GND NC NC CLKT3 VDD VDD CLKC4 GND GND 40 GND 1 VDD ICS95V857 VDD GND 10 11 40-Pin MLF CLKC5 CLKT5 CLKT6 CLKC6 GND GND CLKC7 CLKT7 VDD PD# FB_INC FB_INT FB_OUTC VDD GND FB_OUTT ...
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... FB_INC) provide high-performance, low-skew, low-jitter, output differential clocks (CLKT[0:9], CLKC[0:9]). The ICS95V857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI. The ICS95V857 is characterized for operation from 0°C to 85°C, and will meet JEDEC Standard 82-1 and 82-1A Class A+ for registered DDR clock drivers. ...
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... ICS95V857 Absolute Maximum Ratings Supply Voltage (VDD & AVDD -0.5V to 4.6V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND –0 Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...
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... Differential cross-point voltage is expected to track variations of V voltage at which the differential signal must be crossing. 0674U—01/27/09 CONDITIONS CLKT, CLKC, FB_INC PD# CLKT, CLKC, FB_INC CLKT, FB_INT AC - CLKT, FB_INT ICS95V857 MIN TYP MAX 2.3 2.5 2.7 0 0.18 DD -0.3 0 0.18 2 ...
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... ICS95V857 Timing Requirements 85°C; Supply Voltage A A VDD PARAMETER SYMBOL Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization Switching Characteristics (see note 3) PARAMETER SYMBOL Low-to high level propagation delay time High-to low level propagation delay time ...
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... DD V (CLKC) V (CLKC) ICS95V857 GND Figure 1. IBIS Model Output Load DD DD/2 Figure 2. Output Load Test Circuit t c(n) t c(n+1) t jit(cc c(n) ± t c(n+1) Figure 3. Cycle-to-Cycle Jitter 7 ICS95V857 SCOPE (TT (TT) ...
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... ICS95V857 CLK_INC CLK_INT FB_INC FB_INT FB_OUTC FB_OUTT FB_OUTC FB_OUTT FB_OUTC FB_OUTT X 0674U—01/27/09 Parameter Measurement Information large number of samples) Figure 4. Static Phase Offset t (SK_O) Figure 5. Output Skew ...
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... Y , FB_OUTC FB_OUTT X 20% Clock Inputs and Outputs 0674U—01/27/09 Parameter Measurement Information t (hper_n) t (hper_n+ (jit_Hper) (jit_Hper_n) 2xf O Figure 7. Half-Period Jitter 80% Rise t sl Fall t sl Figure 8. Input and Output Slew Rates 9 ICS95V857 80 20% ...
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... ICS95V857 INDEX INDEX AREA AREA 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information XXXX y G (LF) T Designation for tape and reel packaging Lead Free (Optional) Package Type Revision Designator (will not correlate with datasheet revision) ...
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... Reference Do c.: JEDEC P ublicatio n 95, M O-1 53 PLANE PLANE 1 0-0037 aaa C Designation for tape and reel packaging Lead Free (Optional) Package Type L = TSSOP (TVSOP) Revision Designator (will not correlate with datasheet revision) Device Type 11 ICS95V857 In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN -- 1.20 -- 0.05 0.15 .002 ...
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... ICS95V857 Index Area Top View D THERMALLY ENHANCED, VERY THIN, FINE PITCH BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. Source Reference: MLF2™ SE 10-0053 Ordering Information XXXX y K (LF) T Example: 95V857AKLFT 0674U—01/27/09 Seating Plane ...
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... Min/Max 0.35/0.45 Designation for tape and reel packaging Lead Free (Optional) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type 13 ICS95V857 Numeric Designations Numeric Designations for Horizontal Grid for Horizontal Grid Alpha Designations ...