IDT72413 Integrated Device Technology, IDT72413 Datasheet
IDT72413
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IDT72413 Summary of contents
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... Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. CMOS PARALLEL FIFO WITH FLAGS DESCRIPTION: The IDT72413 high-speed First-In/First-Out (FIFO) that loads and empties data on a first-in-first-out basis expandable in bit width. All speed versions are cascad-able in depth. ...
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... IDT72413 CMOS PARALLEL FIFO WITH FLAGS PIN CONFIGURATION GND 10 PLASTIC DIP (P20-1, ORDER CODE: P) SOIC (SO20-2, ORDER CODE: SO) TOP VIEW CAPACITANCE (T = +25° 1.0MHz) A Symbol Parameter Conditions C Input Capacitance ...
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... IDT72413 CMOS PARALLEL FIFO WITH FLAGS OPERATING CONDITIONS (Commercial 5.0V ± 10 0°C to +70° Symbol Parameter (1) t Shift in HIGH Time SIH (1) t Shift in LOW TIme SIL t Input Data Set-up IDS t Input Data Hold Time IDH (1) t Shift Out HIGH Time ...
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... Output Reference Levels Output Load FUNCTIONAL DESCRIPTION: The IDT72413 FIFO is designed using a dual-port RAM architecture as opposed to the traditional shift register approach. This FIFO architecture has a write pointer, a read pointer and control logic, which allow simultaneous read and write operations. The write pointer is incremented by the falling edge of the Shift In (Sl) control ...
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... Output Enable is used to enable the FIFO outputs onto a bus active LOW. ALMOST-FULL/EMPTY FLAG (AF/E) Almost-Full/Empty Flag signals when the FIFO is 7/8 full (56 or more words) or 1/8 from empty (8 or less words). OUTPUTS: DATA OUTPUT (Q Data output lines, three-state. The IDT72413 has a 5-bit output. 1 SIL t IRL Figure 2 ...
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... IDT72413 CMOS PARALLEL FIFO WITH FLAGS ( (1) INPUT DATA NOTES: 1. FIFO is initially full pulse is applied held HIGH soon as IR becomes HIGH the Input Data is loaded into the FIFO. 5. The write pointer is incremented. SI should not go LOW until (t Figure 4 ...
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... IDT72413 CMOS PARALLEL FIFO WITH FLAGS (1) NOTE: 1. FIFO initailly empty (1) MRIRL IR t (1) MRORL MRQ DATA OUTPUTS AF/E NOTE: 1. FIFO is partially full. t SOH SO (1) AF/E SI NOTE: 1. FIFO contains 9 words (one more than Almost-Empty Figure 7. t and t ...
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... IDT72413 CMOS PARALLEL FIFO WITH FLAGS SIH SI t HFH ( NOTE: 1. FIFO contains 55 words (one short of Almost-Full). t SIH SI t HFH ( NOTE: 1. FIFO contains 31 words (one short of Half-Full). WAVEFORM 1 WAVEFORM 2 NOTES: 1. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. ...
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... FIFOs are expandable in width. However, in forming wider words two external gates are required to generate composite Input and Output Ready flags. This requirement is due to the different fall-through times of the FIFOs. SYSTEM 1 ENBL SI INTERRUPT NOTE: 1. Cascading the FIFOs in word width is done by ANDing the IR and OR as shown in Figure 13. Figure 14. Application for IDT72413 for Two Asynchronous Systems ...
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SHIFT IN SI INPUT READY DATA NOTE: 1. FIFOs can be easily cascaded to any desired depth. The handshaking and associated timing between the FIFOs are handled by the inherent timing ...