mt48lc32m8a2 Micron Semiconductor Products, mt48lc32m8a2 Datasheet

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mt48lc32m8a2

Manufacturer Part Number
mt48lc32m8a2
Description
256mb X8, X16 Sdram Addendum
Manufacturer
Micron Semiconductor Products
Datasheet

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SYNCHRONOUS
DRAM
Features
• Supports PC100 and PC133 functionality
• Fully synchronous; all signals registered on positive
• Internal pipelined operation; column address can
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
• Self refresh mode; standard and low power
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
• 64ms, 8,192-cycle refresh
NOTE:
09005aef8147ae33
256Mb x8, x16 SDRAM Addendum.fm - Rev. B 7/04 EN
OPTION
• Configuration
• Package
• Timing (Cycle Time)
• Self Refresh
• Operating Temperature Range
1. Refer to Micron Technical Note: TN-48-05.
2. Off-center parting line.
edge of system clock
be changed every clock cycle
PRECHARGE, and auto refresh modes
16 Meg x 16 ( 4 Meg x 16 x 4 banks)
32 Meg x 8 (8 Meg x 8 x 4 banks)
WRITE Recovery (
t
Plastic Package – OCPL
54-pin TSOP II (400 mil)
54-pin TSOP II (400 mil) Lead-free
6.0ns @ CL = 3
Standard
Commercial (0
WR = “2 CLK”
MT48LC16M16A2TG-6A
1
o
C to +70
Products and specifications discussed herein are subject to change by Micron without notice.
Part Number:
t
WR)
2
o
C)
MARKING
16M16
32M8
None
None
-6A
TG
A2
P
1
Addendum Changes
tain to the x8 and x16 device and should be referenced
for a complete description of SDRAM functionality
and operating modes. However, to meet the faster
speed grades, some of the AC timing parameters are
slightly different. This addendum data sheet will con-
centrate on the key differences required to support the
enhanced speeds.
cations and functionality unless specified herein.
Table 1:
Table 2:
CL = CAS (READ) latency
MT48LC32M8A2 – 8 MEG x 8 x 4 BANKS
MT48LC16M16A2 – 4 MEG x 16 x 4 BANKS
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/dramds
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column
Addressing
GRADE
SPEED
The standard 256Mb SDRAM data sheets also per-
The Micron 256Mb data sheet provides full specifi-
-6A
FREQUENCY
167 MHz
Address Table
Key Timing Parameters
CLOCK
4 Meg x 16 x 4
SDRAM Addendum
16 MEG x 16
8K (A0–A12)
4 (BA0, BA1)
512 (A0–A8)
banks
8K
256Mb: x8, x16
ACCESS
©2004 Micron Technology, Inc. All rights reserved.
CL = 3
TIME
5.4ns
SETUP
TIME
1.5ns
8 Meg x 8 x 4
4 (BA0, BA1)
32 MEG x 8
8K (A0–A12)
1K (A0–A9)
banks
8K
HOLD
TIME
0.8ns

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mt48lc32m8a2 Summary of contents

Page 1

... SDRAM Addendum.fm - Rev. B 7/04 EN Products and specifications discussed herein are subject to change by Micron without notice. MT48LC32M8A2 – 8 MEG BANKS MT48LC16M16A2 – 4 MEG BANKS For the latest data sheet, please refer to the Micron Web site: www.micron.com/dramds ...

Page 2

Table 3: I SPECIFICATIONS AND CONDITIONS DD Notes 11, 13; notes appear in the standard data sheet; V PARAMETER/CONDITION Operating Current: active mode; burst = READ or WRITE (MIN) Standby Current: ...

Page 3

Table 4: Electrical Characteristics and Recommended AC Operating Conditions Notes 11; Notes appear in the standard data sheet AC CHARACTERISTICS PARAMETER Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width ...

Page 4

Table 5: AC Functional Characteristics Notes appear in the standard data sheet. PARAMETER READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay ...

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