NBC12429FA ON Semiconductor, NBC12429FA Datasheet
NBC12429FA
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NBC12429, NBC12429A 3.3V/5V Programmable PLL Synthesized Clock Generator 25 MHz to 400 MHz Description The NBC12429 and NBC12429A are general purpose, Phase−Lock−Loop (PLL) based synthesized clock sources. The VCO will operate over a frequency range of 200 MHz to 400 MHz. ...
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MHz F with 16 MHz Crystal XTAL1 10−20 MHz OSC 5 XTAL2 S_LOAD 7 P_LOAD 27 S_DATA 26 S_CLOCK Table 1. Output Division N[1:0] Output Division +3.3 or 5.0 ...
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S_CLOCK S_DATA S_LOAD PLL_V XTAL1 S_CLOCK 1 S_DATA 2 S_LOAD 3 PLL_V 4 CC PLL_V 5 CC N/C 6 N/C 7 XTAL1 Figure 3. ...
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The following gives a brief description of the functionality of the NBC12429 and NBC12429A Inputs and Outputs. Unless explicitly stated, all inputs are CMOS/TTL compatible with either pullup or pulldown resistors. The PECL outputs are capable of driving two series ...
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Table 4. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Table 5. ...
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Table 6. DC CHARACTERISTICS (V Symbol V Input HIGH Voltage IH LVCMOS/ LVTTL V Input LOW Voltage IL LVCMOS/ LVTTL I Input Current IN V Output HIGH Voltage OH V Output LOW Voltage OL V Output HIGH Voltage OH PECL ...
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Table 8. AC CHARACTERISTICS (V CC (Note 6) Symbol Characteristic F Maximum Input Frequency MAXI F Maximum Output Frequency MAXO t Period Jitter @ 3.3 V jitter(pd) 10000 WFMS (See Table 13 for Typical Values) Period Jitter @ 5.0 V ...
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Table 8. AC CHARACTERISTICS (V (Note 6) Symbol Characteristic t Setup Time s t Hold Time h t Minimum Pulse Width pwMIN DCO Output Duty Cycle Output Rise/Fall r f NOTE: Device will meet the specifications after ...
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Table 9. PROGRAMMING VCO FREQUENCY FUNCTION TABLE WITH 16 MHZ CRYSTAL Á Á Á Á Á Á Á Á Á Á Á Á Á Á VCO 256 Frequency M Á Á Á Á Á Á Á Á Á Á Count ...
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S_CLOCK signal samples the information on the S_DATA line and loads it into a 14 bit shift register. Note that the P_LOAD signal must be HIGH for the serial load operation to function. The Test register is loaded with the ...
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Table 11. FREQUENCY OPERATING RANGE Á Á ...
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Most of the signals available on the TEST output pin are useful only for performance verification of the device itself. However, the PLL bypass mode may be of interest at the board level for functional debug. When T[2:0] is set ...
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Using the On−Board Crystal Oscillator The NBC12429 and NBC12429A feature a fully integrated on−board crystal oscillator to minimize system implementation costs. The oscillator is a series resonant, multivibrator type design as opposed to the more common parallel resonant oscillator design. ...
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The parallel capacitor combination shown ensures that a low impedance path to ground exists for frequencies well above the bandwidth of the PLL ...
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JEDEC specification is 1000 cycles. Both Peak−to−Peak and RMS statistical values were measured. Period Jitter is the edge placement deviation observed over a long period of consecutive cycles compared to the position of the perfect reference clock’s ...
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Table 13. TYPICAL JITTER PERFORMANCE, M Value N Value F in MHz JITTER JITTER JITTER OUT 200 300 400 Period ( RMS 37 100 150 200 300 400 3.3 V, 25°C with 16 MHz Crystal Input ...
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S_DATA S_CLOCK t SETUP Figure 12. Setup and Hold S_DATA t S_LOAD SETUP Figure 13. Setup and Hold M[8:0] N[1:0] P_ LOAD t SETUP Figure 14. Setup and Hold F OUT F OUT Pulse Width Figure 15. Output Duty Cycle ...
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... F Driver Device F Figure 16. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device NBC12429FA NBC12429FAG NBC12429FAR2 NBC12429FAR2G NBC12429FN NBC12429FNG NBC12429FNR2 NBC12429FNR2G NBC12429AFA NBC12429AFAG NBC12429AFAR2 NBC12429AFAR2G NBC12429AFN NBC12429AFNG NBC12429AFNR2 NBC12429AFNR2G NBC12429AMNG NBC12429AMNR4G † ...
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Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...
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0.010 (0.250 NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT ...
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−T− DETAIL −Z− −AB− −AC− SEATING PLANE 0.10 (0.004) AC NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE ...
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... X 0.28 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81− ...