74VHC373 STMicroelectronics, 74VHC373 Datasheet

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74VHC373

Manufacturer Part Number
74VHC373
Description
OCTAL D-TYPE LATCH WITH 3 STATE OUTPUT NON INVERTING
Manufacturer
STMicroelectronics
Datasheet

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DESCRIPTION
The 74VHC373 is an advanced high-speed
CMOS OCTAL D-TYPE LATCH with 3 STATE
OUTPUT NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input
(OE).
PIN CONNECTION AND IEC LOGIC SYMBOLS
June 1999
HIGH SPEED: t
LOW POWER DISSIPATION:
I
HIGH NOISE IMMUNITY:
V
POWER DOWN PROTECTION ON INPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
BALANCED PROPAGATION DELAYS:
t
OPERATING VOLTAGE RANGE:
V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
IMPROVED LATCH-UP IMMUNITY
LOW NOISE: V
CC
PLH
OH
NIH
CC
= 4 A (MAX.) at T
| = I
(OPR) = 2V to 5.5V
= V
2
t
MOS technology.
PHL
OL
NIL
= 8 mA (MIN)
= 28% V
OLP
PD
= 5.0 ns (TYP.) at V
= 0.9V (Max.)
CC
A
(MIN.)
= 25
WITH 3 STATE OUTPUT NON INVERTING
o
C
CC
= 5V
While the LE input is held at a high level, the Q
outputs will follow the data inputs precisely. When
the LE is taken low, the Q outputs will be latched
precisely at the logic level of D input data. While
the (OE) input is low, the 8 outputs will be in a
normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
(Micro Package)
OCTAL D-TYPE LATCH
74VHC373M
M
ORDER CODES :
74VHC373
(TSSOP Package)
74VHC373T
T
1/10

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74VHC373 Summary of contents

Page 1

... PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 373 IMPROVED LATCH-UP IMMUNITY LOW NOISE 0.9V (Max.) OLP DESCRIPTION The 74VHC373 is an advanced high-speed CMOS OCTAL D-TYPE LATCH with 3 STATE OUTPUT NON INVERTING fabricated with sub-micron silicon gate and double-layer metal 2 wiring C MOS technology. This 8 bit D-Type latch is controlled by a latch enable input (LE) and an output enable input (OE) ...

Page 2

... INPUT EQUIVALENT CIRCUIT TRUTH TABLE INPUTS X:DON’T CARE Z: HIGH IMPEDANCE *: Q OUTPUTSARE LATCHED AT THE TIME WHEN THE LEINPUT ISTAKEN LOW LOGIC LEVEL. LOGIC DIAGRAM 2/10 PIN DESCRIPTION PIN No SYMBOL 12, 15, 16 13, 14, ...

Page 3

... A 0 = GND 5.5V or GND GND I CC 74VHC373 Value Unit -0.5 to +7.0 V -0.5 to +7 -65 to +150 C o 300 C Valu e Unit 2 ...

Page 4

... AC ELECTRICAL CHARACTERISTICS (Input t Symb ol Parameter V (V) t Propagation Delay 3.3 PLH t Time PHL 3 5.0 5.0 t Propagation Delay 3.3 PLH t Time 3.3 PHL 5.0 5.0 t Output EnableTime 3.3 PZL t PZH 3.3 5.0 5.0 t Output Disable Time 3.3 PLZ t PHZ 5.0 t Pulse Width (LE) 3.3 w HIGH 5.0 t Setup Time 3.3 s HIGH or LOW 5.0 t Hold Time D toLE 3 ...

Page 5

... orequivalent pulse generator (typically OUT T est Cond ition Min. Typ . 0.6 -0.9 -0.6 3 74VHC373 Value - Max. Min . Max. 0 threshold (V ), f=1MHz. ILD IHD Open V CC GND 5/10 ...

Page 6

... WAVEFORM PROPAGATION DELAYS, LE MINIMUM PULSE WIDTH SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle) 6/10 ...

Page 7

... WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 50% duty cycle) WAVEFORM 3: PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle) 74VHC373 7/10 ...

Page 8

... SO-20 MECHANICAL DATA DIM. MIN. TYP 0. 0.35 b1 0. 12.60 E 10.00 e 1.27 e3 11.43 F 7. 8/10 mm MAX. MIN. 2.65 0.20 0.004 2.45 0.49 0.013 0.32 0.009 45 (typ.) 13.00 0.496 10.65 0.393 7.60 0.291 1.27 0.19 0.75 8 (max.) inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012 0.020 0.512 0.419 0.050 0.450 0.299 0.050 0.029 P013L ...

Page 9

... PIN 1 IDENTIFICATION 1 MAX. MIN. 1.1 0.15 0.002 0.95 0.335 0.30 0.0075 0.2 0.0035 6.6 0.252 6.5 0.246 4.48 0.169 0.70 0.020 74VHC373 inch TYP. MAX. 0.433 0.004 0.006 0.354 0.374 0.0118 0.0079 0.256 0.260 0.252 0.256 0.173 0.176 0.0256 BSC 0.024 0.028 L E 9/10 ...

Page 10

... Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice ...

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