ds90cf383 National Semiconductor Corporation, ds90cf383 Datasheet
ds90cf383
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ds90cf383 Summary of contents
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... LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link— 65 MHz General Description The DS90CF383 transmitter converts 28 bits of CMOS/TTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in par- allel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted ...
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... Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation. www.national.com (Note 1) Package Derating: DS90CF383 ESD Rating (HBM, 1 100 pF) Recommended Operating −0. ...
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Electrical Characteristics Note 2: Typical values are given for V = 3.3V and T CC Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless ...
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... Note 7: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT). Note 8: Recommended pin to signal mapping. Customer may choose to define differently. FIGURE 3. DS90CF383 (Transmitter) LVDS Output Load and Transition Times FIGURE 4. DS90CF383 (Transmitter) Input Clock Transition Time www.national.com ...
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... TCCS measured between earliest and latest LVDS edges TxCLK Differential Low High Edge FIGURE 5. DS90CF383 (Transmitter) Channel-to-Channel Skew FIGURE 6. DS90CF383 (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe) FIGURE 7. DS90CF383 (Transmitter) Clock In to Clock Out Delay DS100033-9 DS100033-10 DS100033-12 5 www ...
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... AC Timing Diagrams (Continued) FIGURE 8. DS90CF383 (Transmitter) Phase Lock Loop Set Time FIGURE 9. Seven Bits of LVDS in Once Clock Cycle FIGURE 10. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs www.national.com DS100033-14 6 DS100033-16 DS100033-17 ...
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... AC Timing Diagrams (Continued) FIGURE 11. Transmitter Power Down Delay FIGURE 12. Transmitter LVDS Output Pulse Position Measurement DS90CF383 Pin Description — FPD Link Transmitter Pin Name I/O No. TxIN I 28 TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE, FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable). ...
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... Description and receiver devices. This change may enable the re- moval supply from the system, and power may be supplied from an existing 3V power source. 2. The DS90CF383 transmitter input and control inputs ac- cept 3.3V TTL/CMOS levels. They are not 5V tolerant. DS90CF383 DS100033-23 Application ...
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... Italiano National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. Order Number DS90CF383MTD NS Package Number MTD56 2. A critical component is any component of a life ...