DS90CR484 National Semiconductor, DS90CR484 Datasheet

no-image

DS90CR484

Manufacturer Part Number
DS90CR484
Description
48-Bit LVDS Channel Link Serializer/Deserializer
Manufacturer
National Semiconductor
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DS90CR484AVJD
Manufacturer:
NS
Quantity:
1 000
Part Number:
DS90CR484AVJD/NOPB
Manufacturer:
NSC
Quantity:
90
Part Number:
DS90CR484AVJD/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DS90CR484AVJDX/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DS90CR484VJD
Manufacturer:
NS
Quantity:
853
Part Number:
DS90CR484VJD
Manufacturer:
NS/国半
Quantity:
20 000
Part Number:
DS90CR484VJD/NOPB
Manufacturer:
NS
Quantity:
277
Part Number:
DS90CR484VJD/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
Part Number:
DS90CR484VJDX/NOPB
Manufacturer:
Texas Instruments
Quantity:
10 000
© 2000 National Semiconductor Corporation
DS90CR483 / DS90CR484
48-Bit LVDS Channel Link Serializer/Deserializer
General Description
The DS90CR483 transmitter converts 48 bits of CMOS/TTL
data into eight LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a ninth LVDS link. Every
cycle of the transmit clock 48 bits of input data are sampled
and transmitted. The DS90CR484 receiver converts the
LVDS data streams back into 48 bits of CMOS/TTL data. At
a transmit clock frequency of 112MHz, 48 bits of TTL data
are transmitted at a rate of 672Mbps per LVDS data channel.
Using a 112MHz clock, the data throughput is 5.38Gbit/s
(672Mbytes/s).
The multiplexing of data lines provides a substantial cable
reduction. Long distance parallel single-ended buses typi-
cally require a ground wire per active signal (and have very
limited noise rejection capability). Thus, for a 48-bit wide
data and one clock, up to 98 conductors are required. With
this Channel Link chipset as few as 19 conductors (8 data
pairs, 1 clock pair and a minimum of one ground) are
needed. This provides an 80% reduction in cable width,
which provides a system cost savings, reduces connector
physical size and cost, and reduces shielding requirements
due to the cables’ smaller form factor.
The 48 CMOS/TTL inputs can support a variety of signal
combinations. For example, 6 8-bit words or 5 9-bit (byte +
parity) and 3 controls.
The DS90CR483/DS90CR484 chipset is improved over prior
generations of Channel Link devices and offers higher band-
width support and longer cable drive with three areas of en-
hancement. To increase bandwidth, the maximum clock rate
is increased to 112 MHz and 8 serialized LVDS outputs are
Generalized Block Diagrams
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
DS100918
provided. Cable drive is enhanced with a user selectable
pre-emphasis feature that provides additional output current
during transitions to counteract cable loading effects. DC
balancing on a cycle-to-cycle basis, is also provided to re-
duce ISI (Inter-Symbol Interference). With pre-emphasis and
DC balancing, a low distortion eye-pattern is provided at the
receiver end of the cable. A cable deskew capability has
been added to deskew long cables of pair-to-pair skew of up
to +/−1 LVDS data bit time (up to 80 MHz Clock Rate). These
three enhancements allow cables 5+ meters in length to be
driven.
The chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
For more details, please refer to the “Applications Informa-
tion” section of this datasheet.
Features
n Up to 5.38 Gbits/sec bandwidth
n 33 MHz to 112 MHz input clock support
n LVDS SER/DES reduces cable and connector size
n Pre-emphasis reduces cable loading effects
n DC balance data transmission provided by transmitter
n Cable Deskew of +/−1 LVDS data bit time (up to 80
n 5V Tolerant TxIN and control input pins
n Flow through pinout for easy PCB design
n +3.3V supply voltage
n Transmitter rejects cycle-to-cycle jitter
n Conforms to ANSI/TIA/EIA-644-1995 LVDS Standard
reduces ISI distortion
MHz Clock Rate)
DS100918-1
February 2000
www.national.com

Related parts for DS90CR484

DS90CR484 Summary of contents

Page 1

... The 48 CMOS/TTL inputs can support a variety of signal combinations. For example, 6 8-bit words or 5 9-bit (byte + parity) and 3 controls. The DS90CR483/DS90CR484 chipset is improved over prior generations of Channel Link devices and offers higher band- width support and longer cable drive with three areas of en- hancement ...

Page 2

Generalized Transmitter Block Diagram Generalized Receiver Block Diagram www.national.com DS100918-2 DS100918-3 2 ...

Page 3

... Current (Note 1) Package Derating: DS90CR483 DS90CR484 ESD Rating: DS90CR483 −0.3V to +4V (HBM, 1.5k , 100pF) −0.3V to +5.5V (EIAJ 200pF) −0. 0.3V) DS90CR484 CC (HBM, 1.5k , 100pF) −0.3V to +3.6V (EIAJ 200pF) −0.3V to +3.6V Recommended Operating Conditions Continuous +150˚C −65˚C to +150˚C Supply Voltage (V Operating Free Air +260˚C ...

Page 4

Electrical Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter LVDS RECEIVER DC SPECIFICATIONS V Differential Input High TH Threshold V Differential Input Low TL Threshold I Input Current IN TRANSMITTER SUPPLY CURRENT ICCTW Transmitter Supply ...

Page 5

Receiver Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter CLHT CMOS/TTL Low-to-High Transition Time, ( Figure data out CMOS/TTL Low-to-High Transition Time, ( Figure clock out CMOS/TTL High-to-Low ...

Page 6

... Note 6: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O. FIGURE 2. DS90CR483 (Transmitter) LVDS Output Load and Transition Times FIGURE 3. DS90CR484 (Receiver) CMOS/TTL Output Load and Transition Times FIGURE 4. DS90CR483 (Transmitter) Input Clock Transition Time FIGURE 5. DS90CR483 (Transmitter) Setup/Hold and High/Low Times www.national.com FIGURE 1. “ ...

Page 7

... AC Timing Diagrams (Continued) FIGURE 6. DS90CR484 (Receiver) Setup/Hold and High/Low Times FIGURE 7. DS90CR483 (Transmitter) Propagation Delay - Latency (Rising Edge Strobe) FIGURE 8. DS90CR484 (Receiver) Propagation Delay - Latency (Rising Edge Strobe) DS100918-16 DS100918-27 DS100918-28 7 www.national.com ...

Page 8

... AC Timing Diagrams FIGURE 9. DS90CR483 (Transmitter) Phase Lock Loop Set Time FIGURE 10. DS90CR484 (Receiver) Phase Lock Loop Set Time www.national.com (Continued) FIGURE 11. Transmitter Power Down Delay 8 DS100918-19 DS100918-20 DS100918-21 ...

Page 9

AC Timing Diagrams (Continued) C — Setup and Hold Time (Internal data sampling window) defined by Rspos (receiver input strobe position) min and max Tppos — Transmitter output pulse position (min and max) RSKM = Cable Skew (type, length) + ...

Page 10

LVDS Interface FIGURE 14. 48 Parallel TTL Data Inputs Mapped to LVDS Outputs www.national.com 10 DS100918-4 ...

Page 11

DS90CR483 Pin Description—Channel Link Transmitter Pin Name I/O No. TxIN I 48 TxOUTP O TxOUTM O TxCLKIN I TxCLKP O TxCLKM PLLSEL I PRE I DS_OPT GND I PLLV I CC PLLGND I ...

Page 12

... DS90CR484 Pin Description—Channel Link Receiver Pin Name I/O RxINP I RxINM I RxOUT O RxCLKP I RxCLKM I RxCLKOUT O PLLSEL I DESKEW GND I PLLV I CC PLLGND I LVDSV I CC LVDSGND I NC Note 10: These receivers have input fail-safe bias circuitry to guarantee a stable receiver output for floating or terminated receiver inputs. Under test conditions re- ceiver inputs will HIGH state ...

Page 13

... Applications Information The DS90CR483/DS90CR484 chipset is improved over prior generations of Channel Link devices and offers higher band- width support and longer cable drive with three areas of en- hancement. To increase bandwidth, the maximum clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided ...

Page 14

... How to configure for cable inter-connect applications: In applications that require the long cable drive capability. The DS90CR483/DS90CR484 chipset is improved over prior generations of Channel Link devices and offers higher band- width support and longer cable drive with the use of DC bal- anced data transmission, pre-emphasis ...

Page 15

Pin Diagram Transmitter - DS90CR483 15 DS100918-6 www.national.com ...

Page 16

... Pin Diagram www.national.com Receiver - DS90CR484 16 DS100918-7 ...

Page 17

... National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. inches (millimeters) unless otherwise noted Dimensions show in millimeters Order Number DS90CR483VJD and DS90CR484VJD NS Package Number VJD100A 2. A critical component is any component of a life ...

Related keywords