DS90UR907Q-EVK/NOPB National Semiconductor, DS90UR907Q-EVK/NOPB Datasheet
DS90UR907Q-EVK/NOPB
Specifications of DS90UR907Q-EVK/NOPB
Related parts for DS90UR907Q-EVK/NOPB
DS90UR907Q-EVK/NOPB Summary of contents
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... MHz 24-bit Color FPD-Link to FPD-Link II Converter General Description The DS90UR907Q converts FPD-Link to FPD-Link II. It trans- lates four LVDS data/control streams and one LVDS clock pair (FPD-Link) into a high-speed serialized interface (FPD- Link II) over a single pair. This serial bus scheme greatly eases system design by eliminating skew problems between ...
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... I, LVDS RxCLKIN LVDS www.national.com DS90UR907Q — Top View Description True LVDS Data Input This pair requires an external 100 Ω termination for standard LVDS levels. Inverting LVDS Data Input This pair requires an external 100 Ω termination for standard LVDS levels. True LVDS Clock Input This pair requires an external 100 Ω ...
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Pin Name Pin # I/O, Type Control and Configuration PDB 23 I, LVCMOS w/ pull-down VODSEL 20 I, LVCMOS w/ pull-down De-Emph 19 I, Analog w/ pull-up MAPSEL 26 I, LVCMOS w/ pull-down CONFIG 10 LVCMOS [1:0] w/ ...
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... LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch DS90UR907QSQ 36–pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch DS90UR907QSQX 36–pin LLP, 6.0 X 6.0 X 0.8 mm, 0.5 mm pitch Note: Automotive Grade (Q) product incorporates enhanced manufacturing and support processes for the automotive market, including defect detection methodologies. Reliability qualification is compliant with the requirements and temperature grades defined in the AEC Q100 standard ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – V (1.8V) DDn Supply Voltage – V DDIO LVCMOS I/O Voltage −0. LVDS Input Voltage −0. Driver Output Voltage Junction Temperature ...
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Symbol Parameter FPD-LINK II LVDS DRIVER DC SPECIFICATIONS V Differential Output Voltage OD Differential Output Voltage V ODp-p (DOUT+) – (DOUT-) ΔV Output Voltage Unbalance OD Offset Voltage – Single-ended & B, Figure 2 Offset ...
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Symbol Parameter FPD-LINK II LVDS OUTPUT t Output Low-to-High Transition HLT Time Figure 4 t Output High-to-Low Transition HLT Time Figure 4 t Ouput Active to OFF Delay, XZD Figure 7 t PLL Lock Time, Figure 6 PLD t Delay ...
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DC and AC Serial Control Bus Characteristics Over 3.3V supply and temperature ranges unless otherwise specified. Symbol Parameter V Input High Level IH V Input Low Level Voltage IL V Input Hysteresis SDA RiseTime ...
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AC Timing Diagrams and Test Circuits FIGURE 1. FPD-Link DC VTH/VTL Definition FIGURE 2. Output Test Circuit FIGURE 3. Output Waveforms FIGURE 4. Output Transition Times 9 30105062 30105046 30105030 30105047 www.national.com ...
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FIGURE 5. FPD-Link Input Jitter Tolerance 10 30105061 ...
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FIGURE 6. Lock Time FIGURE 7. Disable Time FIGURE 8. Latency Delay 11 30105048 30105049 30105010 www.national.com ...
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FIGURE 9. Output Jitter FIGURE 10. Checkerboard Data Pattern FIGURE 11. BIST PASS Waveform FIGURE 12. Serial Control Bus Timing Diagram 12 30105050 30105032 30105052 30105036 ...
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FIGURE 13. Typical IDDT (1.8V Supply) Current as a function of RxCLK 13 30105001 www.national.com ...
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... The Block Diagram is shown at the beginning of this datasheet. DATA TRANSFER The DS90UR907Q transmits a pixel of data in the following format: C1 and C0 represent the embedded clock in the serial stream always HIGH and C0 is always LOW. b[23:0] contain the scrambled RGB data. DCB is the DC-Balanced control bit ...
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... FIGURE 15. Video Control Signal Filter Wavefrom COLOR BIT MAPPING SELECT The DS90UR907Q can be configured to accept 24-bit color (8-bit RGB) with 2 different mapping schemes: LSBs on RxIN FIGURE 16. 8–bit FPD-LInk Mapping: LSB's on RxIN3 30105042 [3] shown in Figure 16 or MSBs on RxIN[3] shown in 17. The mapping scheme is controlled by MAPSEL pin or by Register ...
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... POWER SAVING FEATURES Power Down Feature (PDB) The DS90UR907Q has a PDB input pin to ENABLE or POW- ER DOWN the device. This pin is controlled by the host and is used to save power, disabling the link when the display is not needed. In the POWER DOWN mode, the high-speed driver outputs are both pulled to VDD and present a 0V VOD state. Note – ...
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... See Figure 19 for the BIST mode flow diagram. Step 1: Place the DS90UR907Q in BIST Mode by setting Ser BISTEN = H. The BIST Mode is enabled via the BISTEN pin. An RxCLKIN is required for all the Ser options. When the de- serializer detects the BIST mode pattern and command (DCA and DCB code) the RGB and control signal outputs are shut off ...
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... FIGURE 19. BIST Mode Flow Diagram Optional Serial Bus Control The DS90UR907Q may be configured by the use of a serial control bus that is I2C protocol compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/ strap pins. A write of 01'h to reg_0x00'h will enable/allow con- figuration by registers ...
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... DD Table FIGURE 22. START and STOP Conditions ends with a Stop condition. A READ is shown in and a WRITE is shown in If the Serial Bus is not required, the three pins may be left open (NC). TABLE 4. ID[x] Resistor Value – DS90UR907Q Resistor RID kΩ 0.47 2.7 8.2 Open FIGURE 23. Serial Control Bus — READ FIGURE 24. Serial Control Bus — ...
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ADD ADD Register Name Bit(s) (dec) (hex Ser Config 1 4 Device ID 6 De-Emphasis 7:5 Control 3:0 www.national.com TABLE 5. Serial Bus Control Registers R/W Defa Function ult (bin) 7 R/W 0 Reserved ...
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... TYPICAL APPLICATION CONNECTION Figure 25 shows a typical application of the DS90UR907Q for a 65 MHz 24-bit Color Display Application. The LVDS inputs of the FPD-Link interface require external 100Ω terminations. The LVDS outputs of FPD-Link II require 100 nF AC coupling capacitors to the line ...
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... PDB input signal. TRANSMISSION MEDIA The DS90UR907Q and the companion deserializer chipset is intended to be used in a point-to-point configuration, through a PCB trace, or through twisted pair cable. The DS90UR907Q provide internal terminations providing a clean signaling en- vironment. The interconnect for LVDS should present a dif- FPD-Link ...
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PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the LVDS devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to ...
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Revision History • 03/30/2010 — Initial Release • 04/14/2010 — Update Table 5 Addr 0[4:2] = Reserved' Addr 0[5] = VODSEL www.national.com • 06/22/2010 — Update all final AC and DC parameter limits; Add typical IDDT curve • 07/26/2010 — ...
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Physical Dimensions inches (millimeters) unless otherwise noted 36–pin LLP Package (6 6 0.8 mm, 0.5 mm pitch) NS Package Number SQA36AC 25 www.national.com ...
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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...