ics98ulpa877a Integrated Device Technology, ics98ulpa877a Datasheet
ics98ulpa877a
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ics98ulpa877a Summary of contents
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... CLK_INT CLKC3 CLK_INC CLKT4 CLKC4 V DDQ CLKT5 AGND CLKC5 AV DD CLKT6 V DDQ CLKC6 GND CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 FBOUTT FBOUTC ICS98ULPA877A Advance Information 52-Ball BGA Top View CLKT0 CLKC0 ...
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... FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time t The PLL in ICS98ULPA877A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ...
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... ICS98ULPA877A is available in Commercial Temperature Range (0°C to 70°C) and Industrial Temperature Range (-40°C to +85°C). See Ordering Information for details Function Table ...
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... ICS98ULPA877A Advance Information Absolute Maximum Ratings Supply Voltage (VDDQ & AVDD -0.5V to 2.5V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0. Ambient Operating Temperature . . . . . . . . . . -40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . -65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied ...
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... CONDITIONS , A VDD CLK_INT, CLK_INC, FB_INC, FB_INT IL OE, OS CLK_INT, CLK_INC, FB_INC, FB_INT IH OE CLK_INT, CLK_INC, FB_INC, FB_INT CLK_INT, CLK_INC, FB_INC, FB_INT ICS98ULPA877A Advance Information MIN TYP MAX 1.7 1.8 1.9 0. DDQ 0. DDQ 0. DDQ 0. DDQ -0 0.3 DDQ 0 ...
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... ICS98ULPA877A Advance Information Timing Requirements Commercial 0°C - 70°C; Industrial -40°C - +85°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL Max clock frequency Application Frequency Range Input clock duty cycle CLK stabilization NOTE: The PLL must be able to handle spread spectrum induced skew. ...
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... Input Clock SLr1(i) Output Enable (OE), (OS) SLr1(o) t jit(cc+) t jit(cc-) t (Ø)dyn 2 t SPO ∑ (su) ∑ t (h) t skew 7 ICS98ULPA877A Advance Information (MHz) MIN TYP MAX 4.73 8 160 to 410 5.82 8 160 to 270 -40 40 271 to 410 -30 30 160 to 270 -60 60 271 to 410 - ...
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... DD ICS98ULPA877A Z = 60Ω 2.97" 60Ω 2.97" Yx, FB_OUTC Yx, FB_OUTT 1177D—11/9/07 Parameter Measurement Information V DD ICS98ULPA877A V (CLK) V GND Figure 1: IBIS Model Output Load GND C = 10pF R = 10Ω 120Ω 10Ω 10pF GND Figure 2: Output Load Test Circuit t C(N) ...
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... CLK_INT CLK_INC CLK_INT Yx# Yx Yx, FB_OUTC Yx, FB_OUTT Yx, FB_OUTC Yx, FB_OUTT Yx, FB_OUTC Yx, FB_OUTT 1177D—11/9/07 Parameter Measurement Information t(∅) t(∅)n t(∅ Figure 4: Static Phase Offset t SKEW Figure 5: Output Skew t C( (JIT_PER) C(n) fo Figure 6: Period Jitter 9 ICS98ULPA877A Advance Information t(∅)n+1 ...
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... ICS98ULPA877A Advance Information Yx, FB_OUTC Yx, FB_OUTT 20% Clock Inputs and outputs 1177D—11/9/07 Parameter Measurement Information t JIT(HPER_n JIT(HPER) JIT(HPER_n) 2xfo Figure 7: Half-Period Jitter 80% t SLR Figure 8: Input and Output Slew Rates 10 t JIT(HPER_n+1) 80 20% t SLF V OD ...
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... Y Y# Figure 10: Time Delay Between OE and Clock Output (Y, Y#) 1177D—11/9/07 t(∅) t(∅)dyn Figure 9: Dynamic Phase Offset 50% V DDQ t EN 50% V DDQ 50 DIS 50 ICS98ULPA877A Advance Information t(∅) SSC OFF SSC ON t(∅)dyn t(∅)dyn Y# Y DDQ DDQ ...
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... ICS98ULPA877A Advance Information VIA 1Ω CARD V DDQ GND VIA CARD *Place the 2200pF capacitors close to the PLL. *Use wide traces for PLL Analog power and GND. Connect PLL and caps to AGND trace and connect trace to one GND via (farthest from PLL). ...
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... Lead Free, RoHS Compliant (Optional) Temperature Grade Blank = 0°C to +70°C (Commercial -40°C to +85°C (Industrial) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device 13 ICS98ULPA877A Advance Information Numeric Designations for Horizontal Grid ...
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... Top View D THERMALLY ENHANCED, VERY THIN, FINE PITCH BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. Source Reference: MLF2™ S 10-0053 Ordering Information ICS98ULPA877AKLF-T Example: ICS XXXX LF- T 1177D—11/9/07 Seating Plane A1 A3 Anvil Singulation or Sawn Singulation A C 0.08 ...