IDT71V321 Integrated Device Technology, Inc., IDT71V321 Datasheet
IDT71V321
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IDT71V321 Summary of contents
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... L R/W L (2) INT L NOTES: 1. IDT71V321 (MASTER): BUSY is an output. IDT71V421 (SLAVE): BUSY is input. 2. BUSY and INT are totem-pole outputs. ©2001 Integrated Device Technology, Inc. HIGH SPEED 3. DUAL-PORT STATIC RAM WITH INTERRUPTS MASTER IDT71V321 easily expands data bus width to 16- or-more-bits using SLAVE IDT71V421 On-chip port arbitration logic (IDT71V321 only) BUSY output flag on IDT71V321 ...
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... High Speed 3. Dual-Port Static RAM with Interrupts The IDT71V321/IDT71V421 are high-speed Dual-Port Static RAMs with internal interrupt logic for interprocessor communica- tions. The IDT71V321 is designed to be used as a stand-alone 8-bit Dual-Port RAM "MASTER" Dual-Port RAM together with the IDT71V421 "SLAVE" Dual-Port in 16-or-more-bit memory system ap- plications results in full speed, error-free operation without the need for additional discrete logic ...
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... IDT71V321/71V421S/L High Speed 3. Dual-Port Static RAM with Interrupts Symbol Rating (2) V Terminal Voltage TERM with Respect to GND Operating T A Temperature T Temperature BIAS Under Bias T Storage STG Temperature DC Output I OUT Current NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only ...
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... IDT71V321/71V421S/L High Speed 3. Dual-Port Static RAM with Interrupts Symbol Parameter Dynamic Operating CC SEM = V Current (Both Ports Active MAX Standby Current SB1 R SEM = SEM (Both Ports - TTL R Level Inputs MAX CE I Standby Current = V SB2 "A" (One Port - TTL Active Port Outputs Disabled, ...
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... IDT71V321/71V421S/L High Speed 3. Dual-Port Static RAM with Interrupts Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT BUSY 435 INT Figure 1. AC Output Test Load Sym bol Param eter READ CYCLE t Read Cycle Time ...
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... IDT71V321/71V421S/L High Speed 3. Dual-Port Static RAM with Interrupts ADDRESS PREVIOUS DATA VALID DATA OUT BUSY OUT NOTES and Address is valid prior to the coincidental with CE transition LOW delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations BDD BUSY has no relationship to valid output data ...
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... IDT71V321/71V421S/L High Speed 3. Dual-Port Static RAM with Interrupts Symbol Parameter WRITE CYCLE (5) t Write Cycle Time WC t Chip Enable to End-of-Write EW t Address Valid to End-of-Write AW t Address Set-up Time AS t Write Pulse Width WP t Write Recovery Time WR t Data Valid to End-of-Write DW (1,2) ...
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... IDT71V321/71V421S/L High Speed 3. Dual-Port Static RAM with Interrupts ADDRESS (6) AS R/W DATA (4) OUT DATA IN ADDRESS CE ( R/W DATA IN NOTES must be HIGH during all address transitions write occurs during the overlap ( measured from the earlier R/W going HIGH to the end of the write cycle. ...
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... IDT71V321/71V421S/L High Speed 3. Dual-Port Static RAM with Interrupts Symbol Parameter BUSY Timing (For Master IDT71V321 Only) BUSY Access Time from Address t BAA BUSY Disable Time from Address t BDA BUSY Access Time from Chip Enable t BAC BUSY Disable Time from Chip Enable ...
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... IDT71V321/71V421S/L High Speed 3. Dual-Port Static RAM with Interrupts R/W "A" BUSY "B" R/W "B" NOTES: must be met for both BUSY input (71V421, slave) or output (71V321, master BUSY is asserted on port 'B' blocking R/W ' for the slave version (71V421 All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is oppsite from port "A". ...
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... IDT71V321/71V421S/L High Speed 3. Dual-Port Static RAM with Interrupts Sym bol Param eter INTERRUPT TIM ING et-up Tim rite Rec Tim Inte rrup Tim e INS t Inte rrup Tim e INR NOTES: 1. 'X' in part numbers indicates power rating (S or L). INT ADDR INTERRUPT ADDRESS "A" ...
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... MATCH MATCH (2) NOTES: 1. Pins BUSY and BUSY are both outputs for IDT71V321 (master). Both are inputs L R for IDT71V421 (slave). BUSY outputs on the IDT71V321 are totem-pole slaves the BUSY input internally inhibits writes 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port ...
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... BUSY indication. Any number of slaves to be addressed in the same address range as the master, use the BUSY signal as a write inhibit signal. Thus on the IDT71V321/IDT71V421 SRAMs the BUSY pin is an output if the part is Master (IDT71V321), and the BUSY pin is an input if the part is a Slave (IDT71V421) as shown in Figure 3. = R/W ...
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... IDT71V321/71V421S/L High Speed 3. Dual-Port Static RAM with Interrupts IDT XXXX A 999 Device Type Power Speed Package NOTE: Contact your sales office Industrial temperature range is available for selected speeds, packages and powers. 1. 03/24/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections ...