IDT72V201 IDT [Integrated Device Technology], IDT72V201 Datasheet
IDT72V201
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IDT72V201 Summary of contents
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... IDT72V201 512 x 9-bit organization IDT72V211 1,024 x 9-bit organization IDT72V221 2,048 x 9-bit organization IDT72V231 4,096 x 9-bit organization IDT72V241 8,192 x 9-bit organization IDT72V251 10 ns read/write cycle time 5V input tolerant Read and Write clocks can be independent Dual-Ported zero fall-through time architecture ...
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... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 INDEX PAF 3 PAE 4 5 GND REN1 6 RCLK 7 REN2 TQFP (PR32-1, order code: PF) ...
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... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 Symbol Rating (2) V Terminal Voltage with TERM Respect to GND T Storage Temperature STG I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 (Commercial 3.3 ±0.3V C;Industrial Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time CLK t Clock High Time CLKH ...
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... Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full. The FIFO is configured to have programmable flags when the Write Enable 2/Load (WEN2/LD) is set LOW at Reset (RS = LOW). The IDT72V201/72V211/ 72V221/72V231/72V241/72V251 devices contain four 8-bit offset registers which can be loaded with data on the inputs, or read on the outputs. See Figure 3 for details of the size of the registers and the default values ...
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... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 IDT72V201 - 256 x 9-BIT 8 7 Empty Offset (LSB) Reg. Default Value 007H Full Offset (LSB) Reg. Default Value 007H 8 IDT72V231 - 2,049 x 9-BIT 8 7 Empty Offset (LSB) Reg. ...
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... The Full Flag (FF) will go LOW, inhibiting further write operation, when the device is full reads are performed after Reset (RS), the Full Flag (FF) will go LOW after 256 writes for the IDT72V201, 512 writes for the IDT72V211, 1,024 writes for the IDT72V221, 2,048 writes for the IDT72V231, 4,096 writes for the IDT72V241 and 8,192 writes for the IDT72V251 ...
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... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 REN1, REN2 WEN1 (1) WEN2/LD EF, PAE FF, PAF NOTES: 1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable flag offset registers ...
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... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9 RCLK t t ENS ENH REN1, REN2 OLZ OE WCLK WEN1 WEN2 NOTE: is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between 1 ...
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... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 WRITE WCLK t SKEW1 WEN1 WEN2 (If Applicable) RCLK t ENH t ENS REN1, REN2 OE LOW DATA IN OUTPUT REGISTER 0 8 NOTE: 1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO. ...
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... NOTES PAF offset. 2. 256 - m words in FIFO for IDT72V201, 512 - m words for IDT72V211, 1,024 - m words for IDT72V221, 2,048 - m words for IDT72V231, 4,096 - m words for IDT72V241, 8,192 - m words for IDT72V251. is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and 3 ...
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... IDT72V201/72V211/72V221/72V231/72V241/72V251 3.3V CMOS SyncFIFO™ 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 CLK t t CLKH CLKL WCLK t ENS LD t ENS WEN1 PAE OFFSET (LSB) t CLK t t CLKH CLKL RCLK t ENS LD t ENS REN1, ...
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... FF). The partial status flags (AE and AF) can be detected from any one device. Figure 15 demonstrates a 18-bit word width by using two IDT72V201/72V211/72V221/72V231/72V241/72V251s. Any word width can be attained by adding additional IDT72V201/72V211/ 72V221/72V231/72V241/72V251s. When these devices are in a Width Expansion Configuration, the Read Enable 2 (REN2) control input can be grounded (see Figure 15) ...
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IDT XXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range product for the 15ns is available as a standard device. All other speed grades are available by special order. 01/11/2002 pg. 3. 02/01/2002 pg. 3. CORPORATE HEADQUARTERS ...