IDT72V205 IDT [Integrated Device Technology], IDT72V205 Datasheet
IDT72V205
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IDT72V205 Summary of contents
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... IDT Standard or First Word Fall Through timing Single or double register-buffered Empty and Full flags ...
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... First Word Fall Through mode (FWFT). The XI and XO pins are used to expand the FIFOs. In depth expansion configuration, First Load (FL) is grounded on the first device and set to HIGH for all other devices in the Daisy Chain. The IDT72V205/72V215/72V225/72V235/72V245 are fabricated using IDT’s high-speed submicron CMOS technology. 1 ...
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... In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the outputs. When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default offset at reset is 31 from empty for IDT72V205, 63 from empty for IDT72V215, and 127 from empty for IDT72V225/ 72V235/72V245. ...
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... IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 Symbol Rating V (2) Terminal Voltage TERM with respect to GND T Storage STG Temperature I DC Output Current OUT NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device ...
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... IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 (Commercial: VCC = 3.3V ± 0.3V 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V -40°C to +85°C) Symbol Parameter f Clock Cycle Frequency S t Data Access Time A t Clock Cycle Time ...
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... When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting further write operations reads are performed after a reset, IR will go HIGH after D writes to the FIFO 257 writes for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245 ...
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... NOTES Empty Offset (Default Values : IDT72V205 n = 31, IDT72V215 n = 63, IDT72V225/72V235/72V245 n = 127 Full Offset (Default Values : IDT72V205 m = 31, IDT72V215 m = 63, IDT72V225/72V235/72V245 m = 127 synchronous PAE/PAF configuration is selected , the PAE is asserted and - 0 updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is asserted and updated on the rising edge of WCLK only and not RCLK ...
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... IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 RXI WXI EF/ Single register-buffered Empty Flag Triple register-buffered Output Ready Flag Double register-buffered Empty Flag ( Single register-buffered Empty Flag Single register-buffered ...
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... When OE is disabled (HIGH), the Q output data bus high-impedance state. LOAD (LD) The IDT72V205/72V215/72V225/72V235/72V245 devices contain two 12-bit offset registers with data on the inputs, or read on the outputs. When the Load (LD) pin is set LOW and WEN is set LOW, data on the inputs D0-D11 is written into the Empty Offset register on the first LOW-to-HIGH transition of the Write Clock (WCLK) ...
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... When there is no longer any free space left, IR goes HIGH, inhibiting further write operations. IR will go HIGH after D writes to the FIFO 257 writes for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245 ...
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... IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 REN, WEN, LD (1) FL, RXI, WXI (2) RCLK, WCLK FF/IR EF/OR PAF, WXO/ HF, RXO PAE NOTES: 1. Single device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally. ...
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... IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 RCLK t t ENS ENH REN OLZ OE WCLK WEN NOTES: is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising 1 ...
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... IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 WRITE WCLK (1) t SKEW1 WEN RCLK t ENS t ENH REN OE LOW DATA IN OUTPUT REGISTER 0 17 NOTES: is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising 1 ...
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... IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 CLK t t CLKH CLKL WCLK t ENS LD t ENS WEN PAE OFFSET Figure 11. Write Programmable Registers (IDT Standard and FWFT Modes) t CLK t CLKH RCLK t ENS ...
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... D = maximum FIFO Depth. In IDT Standard Mode 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245. In FWFT Mode 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245. ...
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... IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 WCLK WXO t ENS WEN NOTE: 1. Write to Last Physical Location. RCLK RXO t ENS REN NOTE: 1. Read from Last Physical Location. WXI WCLK RXI RCLK TM t CLKH Note ...
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... IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 COMMERCIAL AND INDUSTRIAL 17 TEMPERATURE RANGES ...
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... IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 COMMERCIAL AND INDUSTRIAL 18 TEMPERATURE RANGES ...
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... D = maximum FIFO Depth. In IDT Standard Mode 256 for the IDT72V205, 512 for the IDT72V215, 1,024 for the IDT72V225, 2,048 for the IDT72V235 and 4,096 for the IDT72V245. In FWFT Mode 257 for the IDT72V205, 513 for the IDT72V215, 1,025 for the IDT72V225, 2,049 for the IDT72V235 and 4,097 for the IDT72V245. ...
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... IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 WRITE WCLK 1 (1) t SKEW1 WEN RCLK t ENH t ENS REN OE LOW DATA IN OUTPUT REGISTER 0 17 NOTES: is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus t 1 ...
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... IDT72V205/72V215/72V225/72V235/72V245 3.3V CMOS SyncFIFO 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 RCLK t t ENH ENS REN t REF OLZ WCLK WEN NOTES: is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus t 1 ...
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... FL RXI WXI 29 demonstrates a 36-word width by using two IDT72V205/72V215/72V225/ 72V235/72V245s. Any word width can be attained by adding additional IDT72V205/72V215/72V225/72V235/72V245s. These FIFOs are in a single Device Configuration when the First Load (FL), Write Expansion In (WXI) and Read Expansion In (RXI) control inputs are configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during reset (Figure 29) ...
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... PROGRAMMABLE FLAGS) These devices can easily be adapted to applications requiring more than 256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth Expansion using three IDT72V205/72V215/72V225/72V235/72V245s. Maximum depth is limited only by signal loading. Follow these steps: 1. The first device must be designated by grounding the First Load (FL) control input ...
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... The resulting configuration provides a total depth equivalent to the sum of the depths associated with each single FIFO. Figure 31 shows a depth expansion using two IDT72V205/72V215/72V225/72V235/72V245 devices. Care should be taken to select FWFT mode during Master Reset for all FIFOs in the depth expansion configuration. The first word written to an empty configuration will pass from one FIFO to the next (“ ...
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XXXXX X XX IDT Device Type Power Speed NOTES: 1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order. 05/02/2001 pgs and 25. ...