MC100LVEL38 ON Semiconductor, MC100LVEL38 Datasheet

MC100LVEL38

Manufacturer Part Number

MC100LVEL38

Description

2 / 4/6 Clock Generation Chip

Manufacturer

ON Semiconductor

Datasheet

1.MC100LVEL38.pdf (7 pages)

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MC100LVEL38

3.3V ECL ÷2, ÷4/6 Clock

Generation Chip

Description

designed explicitly for low skew clock generation applications. The

internal dividers are synchronous to each other, therefore, the common

output edges are all precisely aligned. The device can be driven by either a

differential or single-ended input signal.

will only be enabled/disabled when the internal clock is already in the

LOW state. This avoids any chance of generating a runt clock pulse on the

internal clock when the device is enabled/disabled as can happen with an

asynchronous control. An internal runt pulse could lead to losing

synchronization between the internal divider stages. The internal enable

flip-flop is clocked on the falling edge of the input clock, therefore, all

associated specification limits are referenced to the negative edge of the

clock input.

the ÷2 and the ÷4/6 outputs are both transitioning from a LOW to a

HIGH. This output allows for clock synchronization within the system.

for systems which utilize multiple LVEL38s, the master reset (MR) input

must be asserted to ensure synchronization. For systems which only use

one LVEL38, the MR pin need not be exercised as the internal divider

design ensures synchronization between the ÷2 and the ÷4/6 outputs of a

single device.

this device only. For single-ended input conditions, the unused

differential input is connected to V

and V

to 0.5 mA. When not used, V

Features

•

*For additional information on our Pb−Free strategy and soldering details, please

November, 2006 − Rev. 8

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip

The common enable (EN) is synchronous so that the internal dividers

The Phase_Out output will go HIGH for one clock cycle whenever

Upon startup, the internal flip-flops will attain a random state; therefore,

The V

PECL Mode Operating Range:

NECL Mode Operating Range:

Internal Input 75 kW Pulldown Resistors

Meets or Exceeds JEDEC Spec EIA/JESD78 IC

Latchup Test

50 ps Maximum Output-to-Output Skew

Synchronous Enable/Disable

Master Reset for Synchronization

ESD Protection: >2 kV Human Body Model

The 100 Series Contains Temperature Compensation

may also rebias AC coupled inputs. When used, decouple V

= 3.0 V to 3.8 V with V

= 0 V with V

via a 0.01 mF capacitor and limit current sourcing or sinking

pin, an internally generated voltage supply, is available to

= −3.0 V to −3.8 V

should be left open.

= 0 V

as a switching reference voltage.

www.DataSheet4U.com

•

Moisture Sensitivity Level 1

For Additional Information, see Application Note

AND8003/D

Flammability Rating: UL 94 V−0 @ 0.125 in,

Oxygen Index: 28 to 34

Transistor Count = 388 devices

Pb−Free Packages are Available*

*For additional marking information, refer to

See detailed ordering and shipping information in the package

dimensions section on page 6 of this data sheet.

Application Note AND8002/D.

ORDERING INFORMATION

MARKING DIAGRAM*

http://onsemi.com

AWLYYWWG

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

DW SUFFIX

CASE 751D

SO−20 WB

100LVEL38

Publication Order Number:

MC100LVEL38/D

Related parts for MC100LVEL38

MC100LVEL38 Summary of contents

Page 1

... ECL ÷2, ÷4/6 Clock Generation Chip Description The MC100LVEL38 is a low skew ÷2, ÷4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended input signal ...

Page 2

Warning: All V to Power Supply to guarantee proper operation. CLK CLK EN MR DIVSEL V BB Table 1. PIN DESCRIPTION Pin Function CLK, CLK ECL Diff Clock Inputs ...

Page 3

CLK Q (÷2) Q (÷4) Q (÷6) Phase_Out (÷4) Phase_Out (÷6) Table 3. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I ...

Page 4

Table 4. LVPECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Output ...

Page 5

Table 6. AC CHARACTERISTICS V Symbol Characteristic fmax Maximum Toggle Frequency (Divide Propagation Delay to Output PLH t CLK to Q (Differential) PHL CLK to Q (Single−Ended) CLK to Phase_Out (Differential) CLK to Phase_Out (Single−Ended) t Within-Device ...

Page 6

... ORDERING INFORMATION Device MC100LVEL38DW MC100LVEL38DWG MC100LVEL38DWR2 MC100LVEL38DWR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D − Odd Number Counters Design AND8002/D − ...

Page 7

... DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS DIM MIN MAX A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 12.65 12.95 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0. Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC100LVEL38/D ...

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