MC100LVEP111 ON Semiconductor, MC100LVEP111 Datasheet

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MC100LVEP111

Manufacturer Part Number
MC100LVEP111
Description
Low-Voltage 1:10 Differential LVECL/LVPECL/LVEPECL/HSTL Clock Driver
Manufacturer
ON Semiconductor
Datasheet

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MC100LVEP111
2.5V / 3.3V 1:10 Differential
ECL/PECL/HSTL Clock Driver
Description
designed with clock distribution in mind, accepting two clock sources into
an input multiplexer. The PECL input signals can be either differential or
single-ended (if the V
the LVEP111 is operating under PECL conditions.
Optimal design, layout, and processing minimize skew within a device and
from device to device.
terminate into 50 W even if only one output is being used. If an output
pair is unused, both outputs may be left open (unterminated) without
affecting skew.
operated from a positive V
LVEP111 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. Single-ended CLK input operation is limited to a V
3.0 V in PECL mode, or V
take advantage of the LVEP111's performance to distribute low skew
clocks across the backplane or the board. In a PECL environment, series
or Thevenin line terminations are typically used as they require no
additional power supplies. For more information on using PECL,
designers should refer to Application Note AN1406/D.
Features
© Semiconductor Components Industries, LLC, 2007
October, 2007 - Rev. 14
The MC100LVEP111 is a low skew 1-to-10 differential driver,
The LVEP111 specifically guarantees low output-to-output skew.
To ensure tightest skew, both sides of differential outputs identically
The MC100LVEP111, as with most other ECL devices, can be
with V
with V
85 ps Typical Device-to-Device Skew
20 ps Typical Output-to-Output Skew
Jitter Less than 1 ps RMS
Maximum Frequency > 3 GHz Typical
V
430 ps Typical Propagation Delay
The 100 Series Contains Temperature Compensation
PECL and HSTL Mode Operating Range: V
NECL Mode Operating Range: V
Open Input Default State
LVDS Input Compatible
Fully Compatible with MC100EP111
Pb-Free Packages are Available
BB
Output
EE
EE
= -2.375 V to -3.8 V
= 0 V
BB
output is used). HSTL inputs can be used when
EE
CC
v -3.0 V in NECL mode. Designers can
supply in PECL mode. This allows the
CC
= 0 V
CC
= 2.375 V to 3.8 V
1
CC
*For additional marking information, refer to
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Application Note AND8002/D.
CASE 488AM
MN SUFFIX
CASE 873A
FA SUFFIX
QFN32
LQFP-32
1
A
WL, L
YY, Y
WW, W = Work Week
G
ORDERING INFORMATION
32
http://onsemi.com
= Wafer Lot
= Assembly Location
= Year
= Pb-Free Package
32
Publication Order Number:
1
DIAGRAM*
MARKING
1
AWLYYWWG
MC100LVEP111/D
LVEP111
MC100
LVEP111
ALYWG
MC100

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MC100LVEP111 Summary of contents

Page 1

... To ensure tightest skew, both sides of differential outputs identically terminate into 50 W even if only one output is being used output pair is unused, both outputs may be left open (unterminated) without affecting skew. The MC100LVEP111, as with most other ECL devices, can be operated from a positive V supply in PECL mode. This allows the CC LVEP111 to be used for high performance clock distribution in +3 ...

Page 2

... Pins will default LOW when left open. ** Pins will default to 2/ Table 2. FUNCTION TABLE CLK_SEL MC100LVEP111 Figure 2. QFN-32 Pinout (Top View) http://onsemi.com 2 FUNCTION ECL/PECL/HSTL CLK Input ECL/PECL/HSTL CLK Input ECL/PECL Outputs ECL/PECL Active Clock Select Input Reference Voltage Output Positive Supply ...

Page 3

... MC100LVEP111 Table 3. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Charged Device Model Moisture Sensitivity (Note 1) Flammability Rating Oxygen Index Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D. CLK0 ...

Page 4

... Pb-Free (QFN-32 Only) Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. MC100LVEP111 Condition 1 Condition 2 V ...

Page 5

... Input and output parameters vary 1:1 with V 7. All loading with 2 Single ended input operation is limited min varies 1:1 with IHCMR EE IHCMR input signal. MC100LVEP111 (Note -40°C Min Typ Max Min 60 90 ...

Page 6

... Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. MC100LVEP111 ...

Page 7

... Measured with 750 mV source, 50% duty cycle clock source. All loading with 15. Skew is measured between outputs under identical transitions and conditions on any one device. 16. Device-to-Device skew for identical transitions at identical V 800 700 600 500 400 300 200 100 0 0 MC100LVEP111 = -2.375 to -3 -40°C Min Typ Max 3 325 400 ...

Page 8

... LVTTL Single-Ended Driver V Figure 9. Single-Ended Interface LVCMOS/LVTTL in Interface MC100LVEP111 V CC LVDS Driver GND V CC CML Driver V EE Figure 8. Standard 50 W Load CML in Interface MC100LVEP111 CLKx CLK GND http://onsemi.com MC100LVEP111 0 CLKx 50 W* 100 CLK GND Figure 6. LVDS in Interface MC100LVEP111 CLKx CLK = ...

Page 9

... Application Note AND8020/D - Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVEP111FA MC100LVEP111FAG MC100LVEP111FAR2 MC100LVEP111FARG MC100LVEP111MNG MC100LVEP111MNRG †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D AN1504/D ...

Page 10

... - DETAIL - -AB- SEATING -AC- PLANE 0.10 (0.004) AC MC100LVEP111 PACKAGE DIMENSIONS 32 LEAD LQFP CASE 873A-02 ISSUE C 4X 0.20 (0.008) AB T 0.20 (0.008 DETAIL NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE ...

Page 11

... BSC D2 2.950 3.100 3.250 E 5.00 BSC E2 2.950 3.100 3.250 e 0.500 BSC K 0.200 --- --- L 0.300 0.400 0.500 5.30 3.20 3.20 5. 0.50 PITCH DIMENSIONS: MILLIMETERS ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. MC100LVEP111/D ...

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