MC100LVEP34 ON Semiconductor, MC100LVEP34 Datasheet
MC100LVEP34
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MC100LVEP34 Summary of contents
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... MC100LVEP34 2.5V / 3.3V ECL ÷2, ÷4, ÷8 Clock Generation Chip The MC100LVEP34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The V generated voltage supply, is available to this device only. For single− ...
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Warning: All V to Power Supply to guarantee proper operation. Figure 1. 16−Lead Pinout (Top View) and Logic Diagram Table 1. PIN ...
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Table 3. ATTRIBUTES Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional Moisture Sensitivity ...
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Table 5. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended) IH (Note 4) V Input LOW Voltage (Single−Ended) ...
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Table 6. 100EP DC CHARACTERISTICS, PECL Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended ...
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Table 8. AC CHARACTERISTICS V Symbol Characteristic f Maximum Toggle Frequency max (See Figure max t Propagation CLK to Q0, Q1, Q2 PLH t Delay to Output PHL t RMS Clock Jitter JITTER (See Figure 4. F ...
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There are two distinct functional relationships between the Master Reset and Clock: MR CLK CASE 1: If the MR is de−asserted (H−L), while the Clock is still high, the outputs will follow the second ensuing clock ...
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... Application Note AND8020/D − Termination of ECL Logic Devices.) ORDERING INFORMATION Device MC100LVEP34D MC100LVEP34DG MC100LVEP34DR2 MC100LVEP34DR2G MC100LVEP34DT MC100LVEP34DTG MC100LVEP34DTR2 MC100LVEP34DTR2G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb−Free ...
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Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ...
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G K −T− SEATING PLANE 0.25 (0.010 PACKAGE DIMENSIONS SO−16 D SUFFIX CASE 751B−05 ISSUE J −B− 0.25 (0.010 ...
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... −V− C 0.10 (0.004) −T− SEATING D PLANE 16X 0.36 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS TSSOP−16 CASE 948F−01 ISSUE Ç ...
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... N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 http://onsemi.com 12 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative MC100LVEP34/D ...