SAA7129 Philips Semiconductors, SAA7129 Datasheet
SAA7129
Available stocks
Related parts for SAA7129
SAA7129 Summary of contents
Page 1
... DATA SHEET SAA7128H; SAA7129H Digital video encoder Product specification File under Integrated Circuits, IC22 INTEGRATED CIRCUITS 2000 Mar 08 ...
Page 2
... Analog output voltages 10 PACKAGE OUTLINE 11 SOLDERING 11.1 Introduction to soldering surface mount packages 11.2 Reflow soldering 11.3 Wave soldering 11.4 Manual soldering 11.5 Suitability of surface mount IC packages for wave and reflow soldering methods 12 DEFINITIONS 13 LIFE SUPPORT APPLICATIONS 14 PURCHASE OF PHILIPS I 2000 Mar COMPONENTS 2 Product specification SAA7128H; SAA7129H ...
Page 3
... On-chip crystal oscillator (3rd-harmonic or fundamental crystal) Down mode (low output voltage) or power-save mode of DACs QFP44 package. 2 GENERAL DESCRIPTION The SAA7128H; SAA7129H encodes digital C video data to an NTSC, PAL or SECAM CVBS or S-video signal. Simultaneously, RGB or bypassed but interpolated C -Y The circuit MHz multiplexed digital D1 input port accepts two ITU-R BT ...
Page 4
... Y, C and CVBS without load o(p-p) (peak-to-peak value) R load resistance L LE low frequency integral linearity error lf(i) LE low frequency differential linearity error lf(d) T ambient temperature amb 2000 Mar 08 PARAMETER 4 Product specification SAA7128H; SAA7129H MIN. TYP. MAX. UNIT 3.15 3.3 3.45 V 3.0 3.3 3.6 V 130 150 mA 75 100 mA TTL compatible 1 ...
Page 5
... Acrobat reader. white to force landscape pages to be ... RESET SDA SCL DD(I2C C-BUS 21 SAA7128H INTERFACE SA SAA7129H 2 I C-bus control MP pos MP7 to MP0 SWITCH MP neg C-bus control 44 TTX ...
Page 6
... C-bus voltage; connect C-bus address; LOW selects slave address 88H, HIGH selects slave address ), C (CVBS) and GREEN (Y) outputs R ) signal R ) signal B 6 SAA7128H; SAA7129H DESCRIPTION 2 C-bus supply ) and C (CVBS) outputs R ) and CVBS (CSYNC) outputs B ) and CVBS (CSYNC) outputs B Product specification ...
Page 7
... V SSD1 V DDD1 RCV1 RCV2 MP7 MP6 MP5 2000 Mar SAA7128H 6 SAA7129H Fig.2 Pin configuration. 7 Product specification SAA7128H; SAA7129H DESCRIPTION V SSA3 33 V SSA2 32 V DDA3 31 30 CVBS 29 BLUE V DDA2 28 27 VBS 26 GREEN V DDA1 RED ...
Page 8
... CVBS signal also possible to connect a Philips digital video decoder (SAA7111, SAA7711A, SAA7112 or SAA7151B) to the SAA7128H; SAA7129H. Via the RTCI pin, connected to RTCO of a decoder, information concerning actual subcarrier, PAL-ID and (with SAA7111 and newer types) definite subcarrier phase can be inserted. ...
Page 9
... The resulting output of e.g. ENCODER video PATH recorder e.g. TV RGB PATH MHB576 9 Product specification SAA7128H; SAA7129H Configuration 3 is passed directly to the RGB output, assuming B ENCODER FADER BYPASS PATH RGB PATH Fig.6 Configuration 3. Configuration 4 input is in use; its signal appears both composite ...
Page 10
... The amplitude, beginning and ending of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. Behind the succeeding quadrature modulator, colour in 10-bit resolution is provided on subcarrier. The numeric ratio between Y and C outputs is in accordance with the respective standards. 10 Product specification SAA7128H; SAA7129H ...
Page 11
... DC) for either purpose. Alternatively, the buffers can be ) ONLY switched into 3-state output condition; this allows for ‘wired AND’ing with other 3-state outputs and can also be used as a power-save mode. 11 Product specification SAA7128H; SAA7129H RGB processor and C signals are de-matrixed, individual B R SECAM processor Output interface/DACs ...
Page 12
... It is also possible to set the signal path to blank via this input. From the ITU-R BT.656 data stream, the SAA7128H; SAA7129H decodes only the start of the first line in the odd field. All other information is ignored and may miss. If this kind of slave mode is active, the RCV pins may be switched to output mode ...
Page 13
... Philips Semiconductors Digital video encoder 7.10 Input levels and formats The SAA7128H; SAA7129H expects digital Y, C with levels (digital codes) in accordance with “ITU-R BT.601” . For C and CVBS outputs, deviating amplitudes of the colour difference signals can be compensated by independent gain control setting, while gain for luminance is set to predefined values, distinguishable for 7 ...
Page 14
Bit allocation map Table 3 Slave receiver (slave address 88H) REGISTER FUNCTION SUBADDR Status byte (read only) 00H Null 01H to 25H Wide screen signal 26H Wide screen signal 27H Real-time control, burst start 28H Burst end 29H Copy ...
Page 15
REGISTER FUNCTION SUBADDR Fade factor other 50H 0 Look-up table key colour 2 U 51H LUTU7 Look-up table key colour 2 V 52H LUTV7 Look-up table key colour 2 Y 53H LUTY7 VPS enable, input control 2 54H VPSEN VPS ...
Page 16
REGISTER FUNCTION SUBADDR Trigger control 6DH Multi control 6EH Closed caption, teletext enable 6FH RCV2 output start 70H RCV2 output end 71H MSBs RCV2 output 72H TTX request H start 73H TTX request H delay 74H CSYNC advance, Vsync shift ...
Page 17
... This bit is reserved and must be set to logic 0. 5 WSS13 Wide screen signalling bits: reserved field. 4 WSS12 3 WSS11 2 WSS10 Wide screen signalling bits: subtitles field. 1 WSS9 0 WSS8 2000 Mar 08 SUBADDRESS ACK DATA 0 DESCRIPTION DESCRIPTION DESCRIPTION 17 Product specification SAA7128H; SAA7129H ACK -------- DATA n ACK P ...
Page 18
... Second byte; the MSB of the byte has to carry the CRCC bit, in accordance with the definition of copy generation management system encoding format. 2000 Mar 08 PAL: BS[5: (21H); default value after reset NTSC: BS[5: (19H) PAL: BE[5: (1DH); default value after reset NTSC: BE[5: (1DH) 18 Product specification SAA7128H; SAA7129H DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION ...
Page 19
... GCD[4:0] Gain colour difference of RGB (C (1 application. 2000 Mar 08 DESCRIPTION DESCRIPTION DESCRIPTION , Y and C R DESCRIPTION , Y and Suggested nominal value = 6 (11010b), depending on external Product specification SAA7128H; SAA7129H 16 ) output, ranging from ( output, ranging from ...
Page 20
... Default value of all bytes after reset = 80H. 4DH KEY2UY 2000 Mar 08 DESCRIPTION C -to-RGB dematrix is active; default state after reset -to-RGB dematrix is bypassed B R DESCRIPTION video signal + (1 FADE1) MPEG signal DESCRIPTION video signal + (1 FADE2) LUT values 20 Product specification SAA7128H; SAA7129H ...
Page 21
... FADE2 = 00H: 100% LUT colour, 0% video FADE2 = 3FH: 100% video, 0% LUT colour; this is the default value after reset FADE3 = 00H: 100% MPEG, 0% video FADE3 = 3FH: 100% video, 0% MPEG; this is the default value after reset 21 Product specification SAA7128H; SAA7129H DESCRIPTION DESCRIPTION DESCRIPTION ...
Page 22
... B data is sampled on the rising clock edge; default state after reset B data is sampled on the falling clock edge B data is sampled on the rising clock edge; default state after reset A data is sampled on the falling clock edge A 22 Product specification SAA7128H; SAA7129H ...
Page 23
... Mar 08 0FH = PAL-B/G and data from input ports 3AH = PAL-B/G and data from look-up table 35H = NTSC-M and data from input ports 57H = NTSC-M and data from look-up table 23 Product specification SAA7128H; SAA7129H DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION ...
Page 24
... GAINV[8:0] = 175 (AFH) output subcarrier of V contribution = nominal GAINV[8:0] = 129 (81H) nominal GAINV for SECAM encoding Note 1. All IRE values are rounded up. 2000 Mar 08 DESCRIPTION ENCODING nominal to +2.16 nominal nominal to +2.04 nominal DESCRIPTION ENCODING nominal to +1.55 nominal nominal to +1.46 nominal 24 Product specification SAA7128H; SAA7129H signal; B signal; R ...
Page 25
... MSB of the 9-bit code that sets the variable gain for the C real-time control disable subcarrier phase reset bit from RTCI 1 = enable subcarrier phase reset bit from RTCI (see Fig.22) variable blanking level, see Table 39 25 Product specification SAA7128H; SAA7129H DESCRIPTION signal, see Table 32. B (1) ENCODING DESCRIPTION signal, see Table 34 ...
Page 26
... These 2 bits select the cross-colour reduction filter in luminance; see Table 41 and Fig.10. These 6 bits select the variable blanking level during vertical blanking interval is typically identical to value of BLNNL. no cross-colour reduction cross-colour reduction #1 active cross-colour reduction #2 active cross-colour reduction #3 active 26 Product specification SAA7128H; SAA7129H (1) ENCODING DESCRIPTION DESCRIPTION ...
Page 27
... SAA7111; for timing see Fig.22 amplitude of colour burst; input representation in accordance with “ITU-R BT.601” ; see BSTA[6:0] Table 44 2000 Mar 08 SAA7128H; SAA7129H DESCRIPTION black 100 IRE; default state after reset black 92.5 IRE including 7.5 IRE set-up of black DESCRIPTION 27 Product specification ...
Page 28
... FSC[07:00] is the least significant byte subcarrier frequency (in multiples of line frequency clock frequency (in multiples of line frequency) llc FSC round ------ 2 ; note llc FSC = 569408543 (21F07C1FH). = 1728 FSC = 705268427 (2A098ACBH). llc = 1728 FSC = 681786290 (28A33BB2H). 28 Product specification SAA7128H; SAA7129H ENCODING DESCRIPTION ...
Page 29
... Table 49 Subaddress 6AH BIT SYMBOL L21E[17:10] Second byte of extended data, even field. The MSB of the byte has to carry the parity bit, in accordance with the definition of line 21 encoding format. 2000 Mar 08 SAA7128H; SAA7129H DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 29 Product specification ...
Page 30
... TRCV2 = 1) and as an internal blanking signal. RCV1 Vertical Sync each field; default state after reset Frame Sync (odd/even) Field Sequence, vertical sync every fourth field (PAL = 0), eighth field (PAL = 1) or twelfth field (SECAM = 1) not applicable 30 Product specification SAA7128H; SAA7129H DESCRIPTION FUNCTION ...
Page 31
... RTCI from SAA7111 if bit RTCE = 1; default value after reset 0 1 reset every two lines or SECAM specific if bit SECAM = reset every eight fields 1 1 reset every four fields 2000 Mar 08 SAA7128H; SAA7129H DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 31 Product specification ...
Page 32
... Table 62). Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed. Leading sync slope at CVBS output coincides with leading slope of RCV2 out at RCV2S = 49H. 2000 Mar 08 LUMINANCE PATH DELAY line = (SCCLN[4: for M-systems line = (SCCLN[4: for other systems LINE 21 ENCODING 32 Product specification SAA7128H; SAA7129H DESCRIPTION DESCRIPTION DESCRIPTION ...
Page 33
... Vertical sync shift between RCV1 and RCV2 (switched to output); in master mode it is possible to shift Hsync (RCV2; CBLF = 0) against Vsync (RCV1; SRCV1 = 00) 1 VS_S1 standard value: VS_S[2: VS_S0 2000 Mar 08 PAL: TTXHS[7:0] = 42H NTSC: TTXHS[7:0] = 54H minimum value: TTXHD[7: Product specification SAA7128H; SAA7129H DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION ...
Page 34
... Table 72. FAL[8: coincides with the first field synchronization pulse. first active line = FAL[8: for M-systems first active line = FAL[8: for other systems 34 Product specification SAA7128H; SAA7129H PAL: TTXOVS = 05H; NTSC: TTXOVS = 06H PAL: TTXOVE = 16H; NTSC: TTXOVE = 10H PAL: TTXEVS = 04H; ...
Page 35
... LINE bits. Disabled line = LINEnn (50 Hz field rate). This bit mask is effective only, if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE. 2000 Mar 08 last active line = LAL[8: for M-systems last active line = LAL[8:0] for other systems 35 Product specification SAA7128H; SAA7129H DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION ...
Page 36
... FSEQ 1 = during first field of a sequence (repetition rate: NTSC = 4 fields, PAL = 8 fields, SECAM = 12 fields not first field of a sequence 0 O_E 1 = during even field 0 = during odd field 2000 Mar 08 SAA7128H; SAA7129H DESCRIPTION 36 Product specification ...
Page 37
... SCBW = 1. (2) SCBW = 0. handbook, halfpage (1) SCBW = 1. (2) SCBW = 0. 2000 Mar 08 ( Fig.8 Chrominance transfer characteristic (dB) 0 (1) ( 0.4 0.8 1.2 f (MHz) Fig.9 Chrominance transfer characteristic 2. 37 Product specification SAA7128H; SAA7129H MBE737 (MHz) MBE735 1.6 14 ...
Page 38
... CCRS1 = 1; CCRS0 = 1. (4) CCRS1 = 0; CCRS0 = 0. handbook, halfpage (1) CCRS1 = 0; CCRS0 = 0. 2000 Mar 08 (4) (2) (3) ( Fig.10 Luminance transfer characteristic (dB) ( Fig.11 Luminance transfer characteristic 2. 38 Product specification SAA7128H; SAA7129H MBE736 6 f (MHz) MGD672 14 f (MHz) ...
Page 39
... G v (dB Fig.13 Colour difference transfer characteristic in RGB. 2000 Mar Fig.12 Luminance transfer characteristic in RGB Product specification SAA7128H; SAA7129H MGB708 14 f (MHz) MGB706 14 f (MHz) ...
Page 40
... Philips Semiconductors Digital video encoder handbook, full pagewidth (dB 0.2 handbook, full pagewidth 30 (deg 0.2 2000 Mar 08 0.4 0.6 0.8 Fig.14 Gain of SECAM pre-emphasis. 0.4 0.6 0.8 Fig.15 Phase of SECAM pre-emphasis. 40 Product specification SAA7128H; SAA7129H 1 1.2 1.4 f (MHz) 1 1.2 1.4 f (MHz) MGB705 1.6 MGB704 1.6 ...
Page 41
... Philips Semiconductors Digital video encoder handbook, full pagewidth (dB 0.2 handbook, full pagewidth 80 (deg 0.2 2000 Mar 08 0.4 0.6 0.8 Fig.16 Gain of SECAM anti-Cloche. 0.4 0.6 0.8 Fig.17 Phase of SECAM anti-Cloche. 41 Product specification SAA7128H; SAA7129H 1 1.2 1.4 f (MHz) 1 1.2 1.4 f (MHz) MGB703 1.6 MGB702 1.6 ...
Page 42
... RCV2 input MP input HTRIG = 0 PRCV2 = 0. TRCV2 = 1. ORCV2 = 0. handbook, full pagewidth CVBS output RCV2 output RCV2S = 0. PRCV2 = 0. ORCV2 = 1. 2000 Mar 08 79LCC 82LCC Fig.18 Sync and video input timing. 73LCC Fig.19 Sync and video output timing. 42 Product specification SAA7128H; SAA7129H MHB579 MHB580 ...
Page 43
... HIGH XCLK t rise time r t fall time f Input timing: RCV1, RCV2, MP7 to MP0, RTCI, SA and TTX t input data set-up time SU;DAT t input data hold time HD;DAT 2000 Mar 08 SAA7128H; SAA7129H CONDITIONS MIN. 3.15 3.0 note 3.3 V; note 1 DDD 0.5 2.0 clocks data I/Os at high-impedance ...
Page 44
... Referring to peak-to-peak analog voltages resulting from identical peak-to-peak digital codes. 2000 Mar 08 CONDITIONS 3rd harmonic note 3 note MHz = 3.3 V. The typical voltage swing is 1.35 V, the typical minimum output DDA 44 Product specification SAA7128H; SAA7129H MIN. MAX. UNIT 30 MHz 50 + ...
Page 45
... Mar 08 T LLC1 t HIGH SU; DAT t HD; DAT not MP neg valid not valid Fig.20 Clock data timing (0) Y(0) Fig.21 Functional timing. 45 Product specification SAA7128H; SAA7129H t r not MP pos valid valid C R (0) Y(1) 2.6 V 1.5 V 0.6 V 2.0 V 0.8 V 2.4 V 0.6 V MHB581 C B (2) MGB699 ...
Page 46
... If the colour detection bit is enabled (RTCE = 1; DECCOL = 1) and no colour was detected (colour detection bit = 0), the subcarrier frequency is Y) generated by the SAA7128H; SAA7129H. In the other case (colour detection bit = 1) the subcarrier frequency is evaluated out of FSCPLL increment. If the colour detection bit is disabled (RTCE = 1; ...
Page 47
... TTXOVE) plus all suitable lines of the even field (TTXEVS and TTXEVE) can be used for teletext insertion Fig.23 Teletext timing. 47 Product specification SAA7128H; SAA7129H is the internally used insertion window for i(TTXW) t i(TTXW MHB504 ...
Page 48
... MHz 1 nF for each V DDD X1 3rd harmonic V DDD1 to V DDD3 XTALI XTAL 17, 39 digital SAA7128H inputs and SAA7129H outputs (1) Typical value. 100 (2) For colour bar. 100 3.3 V analog 0.1 F 0.1 F DGND AGND 0.1 F use one capacitor for each V DDA AGND ...
Page 49
... Values for the external series resistors result Table 76 Digital output signals conversion range CVBS, SYNC TIP-TO-PEAK CARRIER (digits) 1016 2000 Mar 08 load. CONVERSION RANGE (peak-to-peak) Y (VBS) SYNC TIP-TO-WHITE BLACK-TO-WHITE AT GDY = GDC = 6 (digits) (digits) 881 49 Product specification SAA7128H; SAA7129H RGB (Y) 712 ...
Page 50
... 2.5 scale (1) ( 0.40 0.25 10.1 10.1 12.9 0.8 0.20 0.14 9.9 9.9 12.3 REFERENCES JEDEC EIAJ 50 SAA7128H; SAA7129H detail 12.9 0.95 1.3 0.15 0.15 0.1 12.3 0.55 EUROPEAN PROJECTION Product specification SOT307 (1) ( ...
Page 51
... If wave soldering is used the following conditions must be observed for optimal results: 2000 Mar 08 SAA7128H; SAA7129H Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. For packages with leads on two sides and a pitch (e): – ...
Page 52
... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Mar 08 SAA7128H; SAA7129H SOLDERING METHOD WAVE not suitable ...
Page 53
... Philips. This specification can be ordered using the code 9398 393 40011. 2000 Mar 08 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 53 Product specification SAA7128H; SAA7129H 2 C patent to use the 2 C specification defined by ...
Page 54
... Philips Semiconductors Digital video encoder 2000 Mar 08 SAA7128H; SAA7129H NOTES 54 Product specification ...
Page 55
... Philips Semiconductors Digital video encoder 2000 Mar 08 SAA7128H; SAA7129H NOTES 55 Product specification ...
Page 56
... Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel ...