AT45DB321D-MU SL383 Atmel, AT45DB321D-MU SL383 Datasheet
AT45DB321D-MU SL383
Specifications of AT45DB321D-MU SL383
Related parts for AT45DB321D-MU SL383
AT45DB321D-MU SL383 Summary of contents
Page 1
... MHz. Its 34,603,008 bits of memory are organized as 8,192 pages of 512 bytes or 528 bytes each. In addition to the main memory, the AT45DB321D also contains two SRAM buffers of 512/528 bytes each. The buffers allow the receiving of data while a page in the main Memory is being reprogrammed, as well as writing a continuous data stream ...
Page 2
... To allow for simple in-system reprogrammability, the AT45DB321D does not require high input voltages for programming. The device operates from a single power supply, 2.7V to 3.6V, for both the program and read operations. The AT45DB321D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
Page 3
... RDY/BUSY and page-to-buffer transfers. The busy status indicates that the Flash memory array and one of the buffers cannot be accessed; read and write operations to the other buffer can still be performed. Device Power Supply: The V ...
Page 4
... RDY/BUSY 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB321D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase operations can be performed at the chip, sector, block or page level ...
Page 5
... Read Commands By specifying the appropriate opcode, data can be read from the main memory or from either one of the two SRAM data buffers. The DataFlash supports RapidS protocols for Mode 0 and Mode 3. Please refer to the “Detailed Bit-level Read Timing” diagrams in this datasheet for details on the clock cycle sequences for each mode ...
Page 6
... When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred AT45DB321D 6 specification. The Continuous Array Read bypasses both data buffers and leaves the specification ...
Page 7
... A main memory page read allows the user to read data directly from any one of the 8,192 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read from the DataFlash standard page size (528 bytes), an opcode of D2H must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and 4 don’ ...
Page 8
... It is necessary that the page in main memory that is being programmed has been previously erased using one of the erase commands (Page Erase or Block Erase). The programming of the page is internally self-timed and should take place in a maximum time of t status register and the RDY/BUSY pin will indicate that the part is busy. AT45DB321D 8 . During this time, EP ...
Page 9
... Buffer to Main Memory Page Program to be utilized at a later time. To perform a page erase in the DataFlash standard page size (528 bytes), an opcode of 81H must be loaded into the device, followed by three address bytes comprised of 1 don’t care bit, 13 page address bits (PA12 - PA0) that specify the page in the main memory to be erased and 10 don’ ...
Page 10
... The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will remain unchanged. Only those sectors that are not protected or locked down will be erased. Note: AT45DB321D 10 PA8/ PA7/ PA6/ PA5/ ...
Page 11
... To perform a main memory page program through buffer for the DataFlash standard page size (528 bytes), a 1-byte opcode, 82H for buffer 1 or 85H for buffer 2, must first be clocked into the device, followed by three address bytes. The address bytes are comprised of 1 don’ ...
Page 12
... Disable Sector Protection commands. If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector pro- tection is desired and if the WP pin is not used. AT45DB321D 12 Byte 1 3DH Enable Sector Protection ...
Page 13
... Enable Sector Protection Period WP Pin Command Not Issued Previously 1 High 2 Low Command Issued During Period 1 3 High 3597M–DFLASH–3/09 time. When the WP pin is deasserted; however, the sector protection WPE 2 Disable Sector Command Protection Command – Issue Command Issue Command X Not Issued Yet ...
Page 14
... Sector Protection Register.: Table 9-2. Sector Number Protected Unprotected Table 9-3. Sectors 0a, 0b Unprotected Protect Sector 0a (Pages 0-7) Protect Sector 0b (Pages 8-127) Protect Sectors 0a (Pages 0-7), 0b (Pages 8-127) Note: AT45DB321D 14 Sector Protection Register Sector 0 (0a, 0b) 0a (Pages 0-7) Bit (1) 1. The default value for bytes 0 through 63 when shipped from Atmel is 00H don’ ...
Page 15
... Register must be clocked in. As described in contains 64 bytes of data bytes must be clocked into the device. The first byte of data cor- responds to sector 0, the second byte corresponds to sector 1, and so on with the last byte of data corresponding to sector 63. 3597M–DFLASH–3/09 Byte 1 3DH Erase Sector Protection Register ...
Page 16
... Command Program Sector Protection Register Figure 9-3. Program Sector Protection Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB321D 16 , during which time the Status Register will indicate that the device is busy Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte 4 Byte 1 ...
Page 17
... Sector Protection Register is reprogrammed), then the application will need to limit this practice. Instead, a combination of temporarily unprotecting individual sectors along with dis- abling sector protection completely will need to be implemented by the application to ensure that the limit of 10,000 cycles is not exceeded. 3597M–DFLASH–3/ Dummy Byte X X ...
Page 18
... Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure 10-1. Sector Lockdown CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB321D 18 Byte 1 3DH Opcode Opcode Opcode Address Byte 2 Byte 3 Byte 4 Bytes ...
Page 19
... Command Read Sector Lockdown Register Note: Figure 10-2. Read Sector Lockdown Register CS SI Opcode SO Each transition represents 8 bits 3597M–DFLASH–3/09 Sector 0 (0a, 0b) (Pages 0-7) Bit 7, 6 details the values read from the Sector Lockdown Register. Sector Lockdown Register xx = Dummy Byte ...
Page 20
... Therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued. Figure 10-3. Program Security Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB321D 20 Security Register • • • One-time User Programmable , during which time the Status Register will indicate that the device is busy. If the device P ...
Page 21
... A page of data can be transferred from the main memory to either buffer 1 or buffer 2. To start the operation for the DataFlash standard page size (528 bytes), a 1-byte opcode, 53H for buffer 1 and 55H for buffer 2, must be clocked into the device, followed by three address bytes com- prised of 1 don’ ...
Page 22
... AT45DB321D 22 ), the status register and the RDY/BUSY pin will indicate that COMP Figure 25-1 (page 45) is recommended ...
Page 23
... The device density is indicated using bits and 2 of the status register. For the AT45DB321D, the four bits are 1101 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
Page 24
... RDPD down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure 12-2. Resume from Deep Power-Down AT45DB321D 24 time. Once the device has entered the Deep Power-down mode, all instructions EDPD CS SI Each transition represents 8 bits time before the device can receive any commands ...
Page 25
... DataFlash standard page size (528 bytes). The “power of 2” page size is a one- time programmable configuration register and once the device is configured for “power of 2” ...
Page 26
... Value Bit 7 Bit 6 Bit 5 Bit 4 00H 14.1.4 Byte 4 – Extended Device Information String Length Byte Count Hex Value Bit 7 Bit 6 Bit 5 Bit 4 00H AT45DB321D 26 Bit 3 Bit 2 Bit 1 Bit Density Code Bit 3 Bit 2 Bit 1 Bit Product Version Code Bit 3 Bit 2 Bit 1 Bit 0 ...
Page 27
... Manufacturer ID codes that are two, three or even four bytes long with the first byte(s) in the sequence being 7FH. A system should detect code 7FH as a “Continuation Code” and continue to read Manufacturer ID bytes. The first non-7FH byte would signify the last byte of Manufacturer ID data. For Atmel (and some other manufacturers), the Manufacturer ID data is comprised of only one byte. 14.2 ...
Page 28
... Buffer 1 to Main Memory Page Program without Built-in Erase Buffer 2 to Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program Through Buffer 1 Main Memory Page Program Through Buffer 2 AT45DB321D 28 Read Commands Program and Erase Commands Opcode D2H E8H 03H ...
Page 29
... Command Buffer 1 Read Buffer 2 Read Main Memory Page Read Continuous Array Read Status Register Read Note: 3597M–DFLASH–3/09 Protection and Security Commands Additional Commands (1) Legacy Commands 1. These legacy commands are not recommended for new designs. Opcode 3DH + 2AH + 7FH + A9H ...
Page 30
... B9h ABh D1h D2h D3h D4h D6h D7h E8h Notes Don’t Care AT45DB321D 30 Address Byte Address Byte N/A N/A N/A N/A N/A N N/A N Address Byte ...
Page 31
... Table 15-7. Detailed Bit-level Addressing Sequence for DataFlash Standard Page Size (528 Bytes) Page Size = 528 bytes Opcode Opcode 03h 0Bh 50h 53h 55h 58h 59h 60h 61h 77h 7Ch 81h 82h 83h 84h 85h 86h 87h 88h 89h 9Fh B9h ...
Page 32
... The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. AT45DB321D 32 . During power-up, the internal Power-on Reset circuitry keeps the device in ...
Page 33
... IH inputs at CMOS levels MHz mA; OUT MHz mA; OUT MHz mA; OUT MHz mA; OUT CMOS levels CMOS levels I 1 -100 µ AT45DB321D -40°C to 85°C 2.7V to 3.6V Min Typ Max 0 0.7 0.4 - 0.2V Units µA µ µA µ ...
Page 34
... Page Programming Time (512/528 bytes Page Erase Time (512/528 bytes Block Erase Time (4,096/4,224 bytes Chip Erase Time CE t Sector Erase Time (262,144/270,336 bytes RESET Pulse Width RST t RESET Recovery Time REC AT45DB321D 34 AT45DB321D Min Typ Max 6.8 6.8 0.1 0 100 ...
Page 35
... SPI Mode 0 and SPI Mode 3, respectively. Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These are similar to waveform 1 and waveform 2, except that output SO is not restricted to become valid during the t imum frequency = 66 MHz) of the RapidS serial case. 3597M–DFLASH–3/09 2.4V AC DRIVING 1.5V LEVELS 0 ...
Page 36
... Waveform 1 – SPI Mode 0 Compatible (for frequencies MHz) CS SCK HIGH IMPEDANCE SO SI 21.2 Waveform 2 – SPI Mode 3 Compatible (for frequencies MHz) CS SCK HIGH 21.3 Waveform 3 – RapidS Mode SCK HIGH IMPEDANCE SO SI 21.4 Waveform 4 – RapidS Mode SCK HIGH AT45DB321D CSS VALID OUT VALID CSS ...
Page 37
... SCK, the host controller should wait until the next falling edge of SCK to latch the data in. Similarly, the host controller should clock its data out on the rising edge of SCK in order to give the DataFlash a full clock cycle to latch the incoming data in on the next rising edge of SCK. ...
Page 38
... Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB Don’t Care 21.8 Command Sequence for Read/Write Operations for Page Size 528 Bytes (Except Status Register Read, Manufacturer and Device ID Read) SI (INPUT) MSB AT45DB321D 38 CMD 8 bits 8 bits 8 bits Page Address Byte/Buffer Address ...
Page 39
... MAIN MEMORY PAGE PROGRAM BUFFER 1 (512/528 BYTES) BUFFER 1 22.1 Buffer Write CS SI (INPUT) CMD 22.2 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page (INPUT) Each transition represents 8 bits 3597M–DFLASH–3/09 FLASH MEMORY ARRAY WRITE I/O INTERFACE SI ...
Page 40
... Main Memory Page Read CS SI (INPUT) CMD SO (OUTPUT) 23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer (INPUT) SO (OUTPUT) AT45DB321D 40 FLASH MEMORY ARRAY MAIN MEMORY READ PAGE READ I/O INTERFACE SO ADDRESS FOR BINARY PAGE SIZE A15-A8 A21-A16 ...
Page 41
... Continuous Array Read (Legacy Opcode E8H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.2 Continuous Array Read (Opcode 0BH SCK OPCODE MSB HIGH-IMPEDANCE SO 3597M–DFLASH–3/09 BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 CMD X X..X, BFA9 ADDRESS BITS 32 DON'T CARE BITS MSB MSB ADDRESS BITS A21 - ...
Page 42
... Continuous Array Read (Low Frequency: Opcode 03H SCK MSB HIGH-IMPEDANCE SO 24.4 Main Memory Page Read (Opcode: D2H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.5 Buffer Read (Opcode D4H or D6H SCK OPCODE MSB HIGH-IMPEDANCE SO AT45DB321D OPCODE ADDRESS BITS A21- MSB ADDRESS BITS 32 DON'T CARE BITS MSB MSB 6 7 ...
Page 43
... Read Sector Protection Register (Opcode 32H SCK SI 0 MSB HIGH-IMPEDANCE SO 24.8 Read Sector Lockdown Register (Opcode 35H SCK SI 0 MSB HIGH-IMPEDANCE SO 3597M–DFLASH–3/ ADDRESS BITS BINARY PAGE SIZE = 15 DON'T CARE + BFA8-BFA0 STANDARD DATAFLASH PAGE SIZE = OPCODE 14 DON'T CARE + BFA9-BFA0 MSB OPCODE DON'T CARE ...
Page 44
... Read Security Register (Opcode 77H SCK MSB HIGH-IMPEDANCE SO 24.10 Status Register Read (Opcode D7H SCK SI 1 MSB HIGH-IMPEDANCE SO 24.11 Manufacturer and Device Read (Opcode 9FH) CS SCK SI HIGH-IMPEDANCE SO Note: Each transition AT45DB321D OPCODE DON'T CARE MSB OPCODE STATUS REGISTER DATA MSB ...
Page 45
... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. 3597M–DFLASH–3/09 START provide address (82H, 85H) ...
Page 46
... Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000 cumulative page erase and program operations have accumulated before rewriting all pages of the sector. See application note AN-4 (“Using Atmel’s Serial DataFlash”) for more details. AT45DB321D 46 START ...
Page 47
... AT45DB321D-MU (3) AT45DB321D-MU-SL954 (4) AT45DB321D-MU-SL955 AT45DB321D-MWU (3) AT45DB321D-MWU-SL954 (4) AT45DB321D-MWU-SL955 AT45DB321D-SU (3) AT45DB321D-SU-SL954 (4) AT45DB321D-SU-SL955 AT45DB321D-TU Notes: 1. The shipping carrier option is not marked on the devices. 2. Standard parts are shipped with the page size set to 528 bytes. The user is able to configure these parts to a 512-byte page size if desired. ...
Page 48
... Packaging Information 27.1 8M1-A – MLF (VDFN) Pin TOP VIEW Pin #1 Notch e (0. BOTTOM VIEW Package Drawing Contact: packagedrawings@atmel.com AT45DB321D 0. TITLE 8M1-A, 8-pad 1.00 mm Body, Thermally Enhanced Plastic Very Thin Dual Flat No Lead Package (VDFN) SIDE VIEW A3 A1 0.08 C COMMON DIMENSIONS ...
Page 49
... MLF (VDFN) D Pin TOP VIEW D1 Pin # BOTTOM VIEW 2325 Orchard Parkway San Jose, CA 95131 R 3597M–DFLASH–3/09 1 Option A Pin #1 Chamfer (C 0.30) Option B e Pin #1 K Notch (0.20 R) TITLE 8MW, 8-pad 1.0 mm Body, Very Thin Dual Flat Package No Lead (MLF) ...
Page 50
... Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the true geometric position. 4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm. Package Drawing Contact: packagedrawings@atmel.com AT45DB321D TOP VIEW ...
Page 51
... E Notes: 1. This package conforms to JEDEC reference MO-183. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion 0.15 mm per side and 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. 2325 Orchard Parkway San Jose, CA 95131 R 3597M–DFLASH–3/09 PIN SEATING PLANE A1 TITLE 28T, 28-lead (8 x 13.4 mm) Plastic Thin Small Outline Package, Type I (TSOP) 0º ...
Page 52
... Changed the Product Version Code to 00001. Corrected typographical errors. Added errata regarding Chip Erase. Added AT45DB321D-SU to ordering information and corresponding 8S2 package. Removed “not recommended for new designs” note from ordering information for 8MW package. Added AT45DB321D-CNU to ordering information and corresponding 8CN3 package. Removed “ ...
Page 53
... Use Block Erase (opcode 50H alternative. The Block Erase function is not affected by the Chip Erase issue. 29.1.3 Resolution The Chip Erase feature may be fixed with a new revision of the device. Please contact Atmel for the estimated availability of devices with the fix. 3597M–DFLASH–3/09 53 ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...