AT45DB081D-MU-SL954 ATMEL [ATMEL Corporation], AT45DB081D-MU-SL954 Datasheet
AT45DB081D-MU-SL954
Related parts for AT45DB081D-MU-SL954
AT45DB081D-MU-SL954 Summary of contents
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... Green (Pb/Halide-free/RoHS Compliant) Packaging Options 1. Description The AT45DB081D is a 2.5V or 2.7V, serial-interface Flash memory ideally suited for a wide variety of digital voice-, image-, program code- and data-storage applications. The AT45DB081D supports RapidS serial interface for applications requiring very high speed operations. RapidS serial interface is SPI compatible for frequencies MHz ...
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... To allow for simple in-system reprogrammability, the AT45DB081D does not require high input voltages for programming. The device operates from a single power supply, 2.5V to 3.6V or 2.7V to 3.6V, for both the program and read operations. The AT45DB081D is enabled through the chip select pin (CS) and accessed via a three-wire interface consisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK) ...
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Table 2-1. Pin Configurations Symbol Name and Function Chip Select: Asserting the CS pin selects the device. When the CS pin is deasserted, the device will be deselected and normally be placed in the standby mode (not Deep Power-Down mode), ...
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... GND 4. Memory Array To provide optimal flexibility, the memory array of the AT45DB081D is divided into three levels of granularity comprising of sectors, blocks, and pages. The “Memory Architecture Diagram” illustrates the breakdown of each level and details the number of pages per sector and block. All program operations to the DataFlash occur on a page by page basis. The erase operations can be performed at the chip, sector, block or page level ...
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... The first 12 bits (A19 - A8) of the 20-bits sequence specify which page of the main memory array to read, and the last 8 bits (A7 - A0) of the 20-bits address sequence specify the starting byte address within the page. The don’t care bytes that follow the address bytes are needed to initialize the read operation. Following the don’ ...
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... When the end of a page in the main memory is reached during a Continuous Array Read, the device will continue reading at the beginning of the next page with no delays incurred AT45DB081D 6 specification. The Continuous Array Read bypasses both data buffers and leaves the specification ...
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... Main Memory Page Read A main memory page read allows the user to read data directly from any one of the 4,096 pages in the main memory, bypassing both of the data buffers and leaving the contents of the buffers unchanged. To start a page read from the DataFlash standard page size (264 bytes), an opcode of D2H must be clocked into the device followed by three address bytes (which comprise the 24-bit page and byte address sequence) and 4 don’ ...
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... It is necessary that the page in main memory that is being programmed has been previously erased using one of the erase commands (Page Erase or Block Erase). The programming of the page is internally self-timed and should take place in a maximum time of t status register will indicate that the part is busy. AT45DB081D 8 . During this time, EP ...
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... A8) that specify the page in the main memory to be erased and 8 don’t care bits. When a low-to-high transition occurs on the CS pin, the part will erase the selected page (the erased state is a logical 1) ...
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... The erase operation is internally self-timed and should take place in a time of t The Chip Erase command will not affect sectors that are protected or locked down; the contents of those sectors will remain unchanged. Only those sectors that are not protected or locked down will be erased. AT45DB081D 10 PA7/ PA6/ PA5/ ...
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... The address bytes are comprised of 3 don’t care bits, 12 page address bits, (PA11 - PA0) that select the page in the main memory where data written, and 9 buffer address bits (BFA8 - BFA0) that select the first byte in the buffer to be written. To perform a ...
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... Disable Sector Protection commands. If the device is power cycled, then the software controlled protection will be disabled. Once the device is powered up, the Enable Sector Protection command should be reissued if sector pro- tection is desired and if the WP pin is not used. AT45DB081D 12 Byte 1 3DH Enable Sector Protection ...
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Hardware Controlled Protection Sectors specified for protection in the Sector Protection Register and the Sector Protection Reg- ister itself can be protected from program and erase operations by asserting the WP pin and keeping the pin in its asserted ...
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... Sector Protection Register.: Table 9-2. Sector Number Protected Unprotected Table 9-3. Sectors 0a, 0b Unprotected Protect Sector 0a Protect Sector 0b (Page 8-255) Protect Sectors 0a (Page 0-7), 0b (Page 8-255) Note: AT45DB081D 14 Sector Protection Register Sector 0 (0a, 0b) 0a (Page 0-7) Bit (1) 1. The default value for bytes 0 through 15 when shipped from Atmel x = don’ ...
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Erase Sector Protection Register Command In order to modify and change the values of the Sector Protection Register, it must first be erased using the Erase Sector Protection Register command. To erase the Sector Protection Register, the CS pin ...
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... Command Program Sector Protection Register Figure 9-3. Program Sector Protection Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB081D 16 , during which time the Status Register will indicate that the device is busy Opcode Opcode Opcode Data Byte Byte 2 Byte 3 Byte 4 Section 9 ...
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Read Sector Protection Register Command To read the Sector Protection Register, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode of 32H and 3 dummy bytes must be clocked in via the ...
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... Sector Lockdown Register to determine the status of the appropriate sector lockdown bits or bytes and reissue the Sector Lockdown com- mand if necessary. Command Sector Lockdown Figure 10-1. Sector Lockdown CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB081D 18 Byte 1 3DH Opcode Opcode Opcode Address Byte 2 Byte 3 Byte 4 Bytes ...
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... Reading the Sector Lockdown Register The Sector Lockdown Register can be read to determine which sectors in the memory array are permanently locked down. To read the Sector Lockdown Register, the CS pin must first be asserted. Once the CS pin has been asserted, an opcode of 35H and 3 dummy bytes must be clocked into the device via the SI pin ...
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... Therefore, the contents of the buffer 1 will be altered from its previous state when this command is issued. Figure 10-3. Program Security Register CS Opcode SI Byte 1 Each transition represents 8 bits AT45DB081D 20 Security Register • • • One-time User Programmable , during which time the Status Register will indicate that the device is busy. If the device P ...
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Reading the Security Register The Security Register can be read by first asserting the CS pin and then clocking in an opcode of 77H followed by three dummy bytes. After the last don’t care bit has been clocked in, ...
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... The operation is internally self-timed and should take place in a maximum time of t During this time, the status register will indicate that the part is busy. AT45DB081D 22 ), the status register can be read to determine whether the XFR ), the status register will indicate that the part is busy ...
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... The device density is indicated using bits and 2 of the status register. For the AT45DB081D, the four bits are 1001 The decimal value of these four binary bits does not equate to the device density; the four bits represent a combinational code relating to differing densities of DataFlash devices ...
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... RDPD down, the device will return to the normal standby mode. Command Resume from Deep Power-down Figure 12-2. Resume from Deep Power-Down AT45DB081D 24 time. Once the device has entered the Deep Power-down mode, all instructions EDPD CS SI Each transition represents 8 bits time before the device can receive any commands ...
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... Configuration Register is a user-programmable nonvolatile regis- ter that allows the page size of the main memory to be configured for binary page size (256 bytes) or DataFlash standard page size (264 bytes). The “power of 2” page size is a one- time programmable configuration register and once the device is configured for “ ...
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... Byte 4 – Extended Device Information String Length Byte Count Hex Value Bit 7 Bit 6 Bit 5 Bit 4 00H AT45DB081D 26 Bit 3 Bit 2 Bit 1 Bit Density Code Bit 3 Bit 2 Bit 1 Bit Product Version Code Bit 3 Bit 2 ...
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... Chip Erase 5. Main Memory Page to Buffer 1 (or 2) Transfer 6. Main Memory Page to Buffer 1 (or 2) Compare 7. Buffer 1 ( Main Memory Page Program with Built-in Erase 8. Buffer 1 ( Main Memory Page Program without Built-in Erase 9. Main Memory Page Program through Buffer 1 ( ...
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... Buffer 1 to Main Memory Page Program without Built-in Erase Buffer 2 to Main Memory Page Program without Built-in Erase Page Erase Block Erase Sector Erase Chip Erase Main Memory Page Program Through Buffer 1 Main Memory Page Program Through Buffer 2 AT45DB081D 28 Read Commands Program and Erase Commands Opcode D2H E8H 03H ...
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... Table 15-4. Command Main Memory Page to Buffer 1 Transfer Main Memory Page to Buffer 2 Transfer Main Memory Page to Buffer 1 Compare Main Memory Page to Buffer 2 Compare Auto Page Rewrite through Buffer 1 Auto Page Rewrite through Buffer 2 Deep Power-down Resume from Deep Power-down Status Register Read Manufacturer and Device ID Read Table 15-5 ...
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... D7h E8h Notes Don’t Care AT45DB081D 30 Address Byte Address Byte ...
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Table 15-7. Detailed Bit-level Addressing Sequence for the DataFlash Standard Page Size (264 Bytes) Page Size = 264 bytes Opcode Opcode 03h 0Bh 50h ...
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... The regulator needs to supply this peak current requirement. An under specified regulator can cause current starvation. Besides increasing system noise, current starvation during program- ming or erase can lead to improper operation and possible data corruption. AT45DB081D 32 . During power-up, the internal Power-on Reset circuitry keeps the device in ...
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... Note: 1. After power is applied and V tional mode is started. 3596L–DFLASH–04/09 *NOTICE: + 0.6V CC AT45DB081D (2.5V Version) Ind. -40°C to 85°C 2. the minimum specified datasheet value, the system should wait 10 ms before an opera- CC Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent dam- age to the device. The " ...
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... V Output Low Voltage OL V Output High Voltage OH Notes during a buffer read maximum @ 20 MHz. CC1 2. All inputs (SI, SCK, CS#, WP#, and RESET#) are guaranteed by design to be 5-Volt tolerant. AT45DB081D 34 Condition Min CS, RESET all IH inputs at CMOS levels CS, RESET all IH inputs at CMOS levels MHz ...
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... Page Erase Time (256/264 bytes Block Erase Time (2,048/2,112 bytes Sector Erase Time (65,536/67,584 Chip Erase Time CE t RESET Pulse Width RST t RESET Recovery Time REC 3596L–DFLASH–04/09 AT45DB081D (2.5V Version) AT45DB081D Min Typ Max Min 6.8 6.8 6.8 6.8 0.1 0.1 0.1 0 ...
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... SPI Mode 0 and SPI Mode 3, respectively. Waveform 3 and waveform 4 illustrate general timing diagram for RapidS serial interface. These are similar to waveform 1 and waveform 2, except that output SO is not restricted to become valid during the t imum frequency = 66 MHz) of the RapidS serial case. AT45DB081D 36 2.4V AC DRIVING 1 ...
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Waveform 1 – SPI Mode 0 Compatible (for Frequencies MHz) CS SCK HIGH IMPEDANCE SO SI 21.2 Waveform 2 – SPI Mode 3 Compatible (for Frequencies MHz) CS SCK HIGH ...
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... Last bit of BYTE-MOSI is clocked out from the Master. E. Last bit of BYTE-MOSI is clocked into the slave. F. Slave clocks out first bit of BYTE-SO. G. Master clocks in first bit of BYTE-SO. H. Slave clocks out second bit of BYTE-SO. I. Master clocks in last bit of BYTE-SO. AT45DB081D ...
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Reset Timing CS SCK RESET SO (OUTPUT) SI (INPUT) Note: The CS signal should be in the high state before the RESET signal is deasserted. 21.7 Command Sequence for Read/Write Operations for Page Size 256 Bytes (Except Status Register ...
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... Buffer Write CS SI (INPUT) CMD 22.2 Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page (INPUT) Each transition represents 8 bits AT45DB081D 40 FLASH MEMORY ARRAY BUFFER TO MAIN MEMORY PAGE PROGRAM BUFFER (256/264 BYTES) BUFFER WRITE I/O INTERFACE SI BINARY PAGE SIZE ...
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... PAGE TO BUFFER 1 BUFFER 1 (256/264 BYTES) BUFFER 1 23.1 Main Memory Page Read CS SI (INPUT) CMD SO (OUTPUT) 23.2 Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer (INPUT) SO (OUTPUT) 3596L–DFLASH–04/09 FLASH MEMORY ARRAY MAIN MEMORY READ PAGE READ I/O INTERFACE SO ...
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... MSB HIGH-IMPEDANCE SO 24.2 Continuous Array Read (Opcode 0BH SCK OPCODE MSB HIGH-IMPEDANCE SO AT45DB081D 42 BINARY PAGE SIZE 15 DON'T CARE + BFA8-BFA0 CMD X X..X, BFA9-8 BFA7 ADDRESS BITS 32 DON'T CARE BITS ...
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... Continuous Array Read (Low Frequency: Opcode 03H SCK MSB HIGH-IMPEDANCE SO 24.4 Main Memory Page Read (Opcode: D2H SCK OPCODE MSB HIGH-IMPEDANCE SO 24.5 Buffer Read (Opcode D4H or D6H SCK OPCODE ...
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... Read Sector Protection Register (Opcode 32H SCK MSB HIGH-IMPEDANCE SO 24.8 Read Sector Lockdown Register (Opcode 35H SCK MSB HIGH-IMPEDANCE SO AT45DB081D ADDRESS BITS BINARY PAGE SIZE = 16 DON'T CARE + BFA7-BFA0 STANDARD DATAFLASH PAGE SIZE = OPCODE 15 DON'T CARE + BFA8-BFA0 ...
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Read Security Register (Opcode 77H SCK SI 0 MSB HIGH-IMPEDANCE SO 24.10 Status Register Read (Opcode D7H SCK SI 1 MSB HIGH-IMPEDANCE SO 24.11 Manufacturer and Device Read (Opcode 9FH) CS SCK SI HIGH-IMPEDANCE SO ...
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... A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer to Main Memory Page Program operation. 3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page within the entire array. AT45DB081D 46 START provide address ...
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... Figure 25-2. Algorithm for Randomly Modifying Data MAIN MEMORY PAGE PROGRAM THROUGH BUFFER (82H, 85H) Notes preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000 cumulative page erase and program operations Page Address Pointer must be maintained to indicate which page rewritten. The Auto Page Rewrite command must use the address specified by the Page Address Pointer ...
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... Ordering Information 26.1 Ordering Code Detail Atmel Designator Product Family Device Density 8 = 8-megabit Interface 1 = Serial Device Revision 26.2 Green Package Options (Pb/Halide-free/RoHS Compliant) (1)(2) Ordering Code AT45DB081D-MU (3) AT45DB081D-MU-SL954 (4) AT45DB081D-MU-SL955 AT45DB081D-SSU (3) AT45DB081D-SSU-SL954 (4) AT45DB081D-SSU-SL955 AT45DB081D-SU (3) AT45DB081D-SU-SL954 (4) AT45DB081D-SU-SL955 AT45DB081D-MU-2.5 AT45DB081D-SSU-2.5 AT45DB081D-SU-2.5 Notes: 1. The shipping carrier option is not marked on the devices. ...
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Packaging Information 27.1 8M1-A – MLF (VDFN) Pin TOP VIEW Pin #1 Notch BOTTOM VIEW Package Drawing Contact: packagedrawings@atmel.com 3596L–DFLASH–04/ 0.45 (0. TITLE ...
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... JEDEC SOIC TOP VIEW e e SIDE VIEW Note: These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 R AT45DB081D ...
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EIAJ SOIC e e Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information. 2. Mismatch of the upper and lower dies and resin burrs aren't included. 3. Determines the ...
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... G – January 2008 H – January 2008 I – April 2008 J – February 2009 K – March 2009 L - April 2009 AT45DB081D 52 History Initial Release Added Preliminary. Added text, in “Programming the Configuration Register”, to indicate that power cycling is required to switch to “power of 2” page size after the opcode enable has been executed. Added “ ...
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Errata 29.1 No Errata Conditions 3596L–DFLASH–04/09 53 ...
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Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to ...