CXA1616S

Manufacturer Part NumberCXA1616S
ManufacturerSony
CXA1616S datasheet
 


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Pin No.
Symbol
Pin voltage
SDIP
SSOP
6
EHC
6
3.0, 4.8V
VIDEO IN
7
7
4.5V
8
HD SEL
8
TIMING
9
9
10.5V
Equivalent circuit
Connects a quasi-peak hold circuit
with a 33kΩ resistance and 0.22µF
V
CC
capacitor to discriminate input signal
200
20k
existence during composite sync input.
When there is a composite sync, the
6
8k
voltage is held by the quasi-peak hold
1k
1k
circuit at 4.2 to 4.8V. This voltage is
3.8V
then compared to a 3.8V reference
12k
voltage, and an input signal is judged
30µA
to exist.
16k
The voltage is 3.0V when no input
signal exists.
Inputs the sync-on video (sync is
negative polarity). Connect a 0.47µF
capacitor and a 270Ω resistance in
series between the pin and its signal
V
CC
source.
8.3V
The slice level is determined by the
5.8V
4k
relationship between the sync
frequency and Pulse width and the
sum of the 200Ω internal resistance
200
and the 270Ω external resistance
7
multiplied by the 29µA current.
∆V ≈ 29µA
16k
72k
29µA
4.5V
Selects whether or not to output the
VD interval portion of HD (H Drive
200k
70k
Pulse).
Input is at TTL Ievel.
1k
8
Low level: The VD interval HD is not
output.
High level or open: The VD interval HD
is output as is.
V
CC
Connect a desired capacitor and a
10k
100
12kΩ resistance in parallel to GND.
This capacitor changes the output
9
pulse width of clamp pulse.
1k
(See Fig. 1)
17k
30µA
– 4 –
CXA1616N/S
Description
(T
/T
)
(200 + 270)
2
1
V
T
T
1
2
V Low ≤ 0.5V
V High ≥ 2.0V