MC68HC705C8ACS

Manufacturer Part NumberMC68HC705C8ACS
DescriptionHCMOS 8-bit microcontroller unit
ManufacturerMotorola
MC68HC705C8ACS datasheet
 

Specifications of MC68HC705C8ACS

CaseDIP-40L  
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
Page 81
82
Page 82
83
Page 83
84
Page 84
85
Page 85
86
Page 86
87
Page 87
88
Page 88
89
Page 89
90
Page 90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
Page 88/222:

Port D

Download datasheet (3Mb)Embed
PrevNext
Parallel Input/Output (I/O)
7.6 Port D
Port D is a 7-bit, special-purpose, input-only port that has no data
register. Reading address $0003 returns the logic states of the port D
pins.
Port D shares pins PD5–PD2 with the serial peripheral interface module
(SPI). When the SPI is enabled, PD5–PD2 read as logic 0s. When the
SPI is disabled, reading address $0003 returns the logic states of the
PD5–PD2 pins.
Port D shares pins PD1 and PD0 with the SCI module. When the SCI is
enabled, PD1 and PD0 read as logic 0s. When the SCI is disabled,
reading address $0003 returns the logic states of the PD1 and PD0 pins.
Address:
Read:
Write:
Reset:
Technical Data
88
$0003
Bit 7
6
5
4
PD7
SS
SCK
Unaffected by reset
= Unimplemented
Figure 7-10. Port D Fixed Input Register (PORTD)
Parallel Input/Output (I/O)
3
2
1
Bit 0
MOSI
MISO
TDO
RDI
MC68HC705C8A — Rev. 3
MOTOROLA