MC68HC705C8ACS

Manufacturer Part NumberMC68HC705C8ACS
ManufacturerFreescale Semiconductor, Inc
MC68HC705C8ACS datasheet
 


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Freescale Semiconductor, Inc.
11.9.3 SPI Status Register
The SPSR shown in
conditions:
Address:
Read:
Write:
Reset:
SPIF — SPI Flag
This clearable, read-only bit is set each time a byte shifts out of or into
the shift register. SPIF generates an interrupt request if the SPIE bit
in the SPCR is also set. Clear SPIF by reading the SPSR with SPIF
set and then reading or writing the SPDR. Reset clears the SPIF bit.
WCOL — Write Collision Bit
This clearable, read-only flag is set when software writes to the SPDR
while a transmission is in progress. Clear the WCOL bit by reading the
SPSR with WCOL set and then reading or writing the SPDR. Reset
clears WCOL.
MC68HC705C8A — Rev. 3
MOTOROLA
For More Information On This Product,
Figure 11-9
contains flags to signal these
SPI transmission complete
Write collision
Mode fault
$000B
Bit 7
6
5
4
SPIF
WCOL
MODF
0
0
0
= Unimplemented
Figure 11-9. SPI Status Register (SPSR)
1 = Transmission complete
0 = Transmission not complete
1 = Invalid write to SPDR
0 = No invalid write to SPDR
Serial Peripheral Interface (SPI)
Go to: www.freescale.com
Serial Peripheral Interface (SPI)
SPI I/O Registers
3
2
1
Bit 0
Technical Data