TE28F640J3A-150

Manufacturer Part NumberTE28F640J3A-150
DescriptionTE28F640J3A-150Intel StrataFlash Memory (J3)
ManufacturerIntel Corporation
TE28F640J3A-150 datasheet
 
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Page 49/72:

Array Protection

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Table 21. Byte-Wide Protection Register Addressing (Sheet 2 of 2)
6
Factory
7
Factory
8
User
9
User
A
User
B
User
C
User
D
User
E
User
F
User
NOTE: All address lines not specified in the above table must be 0 when accessing the Protection Register,
i.e.g., A[MAX:9] = 0.
13.4

Array Protection

The V
signal is a hardware mechanism to prohibit array alteration. When the V
PEN
below the V
PENLK
operation, V
must be set to a valid voltage level. To determine the status of an erase or program
PEN
operation, poll the Status Register and analyze the bits.
Datasheet
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
1
0
0
0
voltage, array contents cannot be altered. To ensure a proper erase or program
256-Mbit J3 (x8/x16)
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
voltage is
PEN
49