TE28F640J3A-150

Manufacturer Part NumberTE28F640J3A-150
DescriptionTE28F640J3A-150Intel StrataFlash Memory (J3)
ManufacturerIntel Corporation
TE28F640J3A-150 datasheet
 
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Revision History

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Revision History

Date of
Version
Revision
07/07/99
-001
08/03/99
-002
09/07/99
-003
12/16/99
-004
03/16/00
-005
06/26/00
-006
2/15/01
-007
04/13/01
-008
Datasheet
Description
Original Version
A
–A
indicated on block diagram
0
2
Changed Minimum Block Erase time,I
OL
currents. Modified RP# on AC Waveform for Write Operations
Changed Block Erase time and t
AVWH
Removed all references to 5 V I/O operation
Corrected Ordering Information, Valid Combinations entries
Changed Min program time to 211 µs
Added DU to Lead Descriptions table
Changed Chip Scale Package to Ball Grid Array Package
Changed default read mode to page mode
Removed erase queuing from Figure 10, Block Erase Flowchart
Added Program Max time
Added Erase Max time
Added Max page mode read current
Moved tables to correspond with sections
Fixed typographical errors in ordering information and DC parameter table
Removed V
setting and changed V
CCQ1
CCQ2/3
Added recommended resister value for STS pin
Change operation temperature range
Removed note that rp# could go to 14 V
Removed V
of 0.45 V; Removed V
OL
OH
Updated I
Typ values
CCR
Added Max lock-bit program and lock times
Added note on max measurements
Updated cover sheet statement of 700 million units to one billion
Corrected Table 10 to show correct maximum program times
Corrected error in Max block program time in section 6.7
Corrected typical erase time in section 6.7
Updated cover page to reflect 100K minimum erase cycles
Updated cover page to reflect 110 ns 32M read speed
Removed Set Read Configuration command from Table 4
Updated Table 8 to reflect reserved bits are 1-7; not 2-7
Updated Table 16 bit 2 definition from R to PSS
Changed V
Max voltage from 0.8 V to 2.0 V, Section 6.4, DC
PENLK
Characteristics
Updated 32Mbit Read Parameters R1, R2 and R3 to reflect 110ns, Section 6.5,
AC Characteristics–Read-Only Operations
Updated write parameter W13 (t
) from 90 ns to 500 ns, Section 6.6, AC
WHRL
Characteristics–Write Operations
Updated Max. Program Suspend Latency W16 (t
Section 6.7, Block Erase, Program, and Lock-Bit Configuration Performance
(1,2,3)
Revised Section 7.0, Ordering Information
Contents
, I
, Page Mode and Byte Mode
OH
to V
CCQ1/2
of 2.4 V
(1,2)
) from 30 to 75 µs,
WHRH1
5