MC68030RC33

Manufacturer Part NumberMC68030RC33
DescriptionMC68030RC33ENHANCED 32-BIT MICROPROCESSOR
ManufacturerMotorola
MC68030RC33 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
Page 151
152
Page 152
153
Page 153
154
Page 154
155
Page 155
156
Page 156
157
Page 157
158
Page 158
159
Page 159
160
Page 160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
Page 152/602:

Data Bus

Download datasheet (4Mb)Embed
PrevNext
Bus Operation
7.1.4 Data Bus
The data bus signals (D0–D31) comprise a bidirectional, nonmultiplexed parallel bus that
contains the data being transferred to or from the processor. A read or write operation may
transfer 8, 16, 24, or 32 bits of data (one, two, three, or four bytes) in one bus cycle. During
a read cycle, the data is latched by the processor on the last falling edge of the clock for that
bus cycle. For a write cycle, all 32 bits of the data bus are driven, regardless of the port width
or operand size. The processor places the data on the data bus one-half clock cycle after
AS is asserted in a write cycle.
7.1.5 Data Strobe
The data strobe (DS) is a timing signal that applies to the data bus. For a read cycle, the
processor asserts DS to signal the external device to place data on the bus. It is asserted at
the same time as AS during a read cycle. For a write cycle, DS signals to the external device
that the data to be written is valid on the bus. The processor asserts DS one full clock cycle
after the assertion of AS during a write cycle.
7.1.6 Data Buffer Enable
The data buffer enable signal (DBEN) can be used to enable external data buffers while data
is present on the data bus. During a read operation, DBEN is asserted one clock cycle after
the beginning of the bus cycle and is negated as DS is negated. In a write operation, DBEN
is asserted at the time AS is asserted and is held active for the duration of the cycle. In a
synchronous system supporting two-clock bus cycles, DBEN timing may prevent its use.
7.1.7 Bus Cycle Termination Signals
During asynchronous bus cycles, external devices assert the data transfer and size
acknowledge signals (DSACK0 and/or DSACK1) as part of the bus protocol. During a read
cycle, the assertion of DSACKx signals the processor to terminate the bus cycle and to latch
the data. During a write cycle, the assertion of DSACKx indicates that the external device
has successfully stored the data and that the cycle may terminate. These signals also
indicate to the processor the size of the port for the bus cycle just completed, as shown in
Table 7-1. Refer to 7.3.1 Asynchronous Read Cycle for timing relationships of DSACK0
and DSACK1.
MOTOROLA
MC68030 USER’S MANUAL
7-5